Simulation Results: lc_ctrl/volatile_unlock_enabled

 
10/08/2026 15:30:36 DVSim: v1.50.1 sha: af43bb2 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.43 %
  • code
  • 83.62 %
  • assert
  • 94.83 %
  • func
  • 92.83 %
  • line
  • 97.17 %
  • branch
  • 93.52 %
  • cond
  • 79.34 %
  • toggle
  • 86.40 %
  • FSM
  • 61.68 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 0.950s 254.658us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 0.940s 52.588us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.820s 37.058us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.090s 83.211us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.310s 63.510us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.200s 537.958us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.820s 37.058us 1 1 100.00
lc_ctrl_csr_aliasing 1.310s 63.510us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 3.440s 164.124us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 5.080s 685.146us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.760s 42.431us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 2.360s 114.422us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 6.560s 689.530us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 5.930s 1592.612us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 6.560s 689.530us 1 1 100.00
lc_ctrl_prog_failure 2.360s 114.422us 1 1 100.00
lc_ctrl_errors 5.930s 1592.612us 1 1 100.00
lc_ctrl_security_escalation 5.210s 2822.262us 1 1 100.00
lc_ctrl_jtag_state_failure 21.600s 2065.149us 1 1 100.00
lc_ctrl_jtag_prog_failure 3.970s 317.288us 1 1 100.00
lc_ctrl_jtag_errors 18.390s 1847.335us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 1.690s 385.509us 1 1 100.00
lc_ctrl_jtag_state_post_trans 5.030s 5409.255us 1 1 100.00
lc_ctrl_jtag_prog_failure 3.970s 317.288us 1 1 100.00
lc_ctrl_jtag_errors 18.390s 1847.335us 1 1 100.00
lc_ctrl_jtag_access 2.810s 449.570us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 9.170s 4648.232us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 1.060s 105.372us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.230s 82.907us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 5.450s 941.960us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 3.830s 566.976us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.020s 71.981us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 1.970s 819.309us 1 1 100.00
lc_ctrl_jtag_alert_test 1.060s 41.461us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 6.020s 3608.486us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.870s 52.063us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 34.960s 13705.880us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 0.840s 66.691us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 1.300s 25.569us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 1.300s 25.569us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.940s 52.588us 1 1 100.00
lc_ctrl_csr_rw 0.820s 37.058us 1 1 100.00
lc_ctrl_csr_aliasing 1.310s 63.510us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.020s 111.917us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.940s 52.588us 1 1 100.00
lc_ctrl_csr_rw 0.820s 37.058us 1 1 100.00
lc_ctrl_csr_aliasing 1.310s 63.510us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.020s 111.917us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 7.090s 1335.104us 1 1 100.00
lc_ctrl_tl_intg_err 1.810s 706.790us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.810s 706.790us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 5.080s 685.146us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 6.560s 689.530us 1 1 100.00
lc_ctrl_sec_cm 7.090s 1335.104us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 6.560s 689.530us 1 1 100.00
lc_ctrl_sec_cm 7.090s 1335.104us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 6.560s 689.530us 1 1 100.00
lc_ctrl_sec_cm 7.090s 1335.104us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 6.560s 689.530us 1 1 100.00
lc_ctrl_sec_cm 7.090s 1335.104us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 6.560s 689.530us 1 1 100.00
lc_ctrl_sec_cm 7.090s 1335.104us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 6.560s 689.530us 1 1 100.00
lc_ctrl_sec_cm 7.090s 1335.104us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 6.560s 689.530us 1 1 100.00
lc_ctrl_sec_cm 7.090s 1335.104us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 6.560s 689.530us 1 1 100.00
lc_ctrl_sec_cm 7.090s 1335.104us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 5.210s 2822.262us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 3.440s 164.124us 1 1 100.00
lc_ctrl_jtag_state_post_trans 5.030s 5409.255us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 6.340s 440.791us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 6.340s 440.791us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 4.200s 329.971us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.670s 3018.688us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.670s 3018.688us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
lc_ctrl_stress_all_with_rand_reset 27.680s 2809.375us 1 1 100.00