Simulation Results: pwrmgr

 
10/08/2026 15:30:36 DVSim: v1.50.1 sha: af43bb2 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.68 %
  • code
  • 95.62 %
  • assert
  • 97.39 %
  • func
  • 97.03 %
  • line
  • 99.09 %
  • branch
  • 96.37 %
  • cond
  • 95.47 %
  • toggle
  • 91.15 %
  • FSM
  • 96.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
pwrmgr_smoke 0.610s 40.566us 1 1 100.00
csr_hw_reset 1 1 100.00
pwrmgr_csr_hw_reset 0.660s 31.690us 1 1 100.00
csr_rw 1 1 100.00
pwrmgr_csr_rw 0.690s 42.139us 1 1 100.00
csr_bit_bash 1 1 100.00
pwrmgr_csr_bit_bash 2.600s 1760.038us 1 1 100.00
csr_aliasing 1 1 100.00
pwrmgr_csr_aliasing 0.850s 113.983us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
pwrmgr_csr_mem_rw_with_rand_reset 1.010s 49.839us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
pwrmgr_csr_rw 0.690s 42.139us 1 1 100.00
pwrmgr_csr_aliasing 0.850s 113.983us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
wakeup 1 1 100.00
pwrmgr_wakeup 0.840s 253.600us 1 1 100.00
control_clks 1 1 100.00
pwrmgr_wakeup 0.840s 253.600us 1 1 100.00
aborted_low_power 2 2 100.00
pwrmgr_aborted_low_power 0.800s 31.649us 1 1 100.00
pwrmgr_lowpower_invalid 0.740s 78.614us 1 1 100.00
reset 2 2 100.00
pwrmgr_reset 0.800s 78.922us 1 1 100.00
pwrmgr_reset_invalid 0.780s 109.428us 1 1 100.00
main_power_glitch_reset 1 1 100.00
pwrmgr_reset 0.800s 78.922us 1 1 100.00
reset_wakeup_race 1 1 100.00
pwrmgr_wakeup_reset 0.830s 153.134us 1 1 100.00
lowpower_wakeup_race 1 1 100.00
pwrmgr_lowpower_wakeup_race 0.910s 378.844us 1 1 100.00
disable_rom_integrity_check 1 1 100.00
pwrmgr_disable_rom_integrity_check 1.220s 156.827us 1 1 100.00
stress_all 1 1 100.00
pwrmgr_stress_all 0.760s 240.564us 1 1 100.00
intr_test 1 1 100.00
pwrmgr_intr_test 0.580s 18.734us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
pwrmgr_tl_errors 1.320s 74.235us 1 1 100.00
tl_d_illegal_access 1 1 100.00
pwrmgr_tl_errors 1.320s 74.235us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
pwrmgr_csr_hw_reset 0.660s 31.690us 1 1 100.00
pwrmgr_csr_rw 0.690s 42.139us 1 1 100.00
pwrmgr_csr_aliasing 0.850s 113.983us 1 1 100.00
pwrmgr_same_csr_outstanding 0.790s 84.393us 1 1 100.00
tl_d_partial_access 4 4 100.00
pwrmgr_csr_hw_reset 0.660s 31.690us 1 1 100.00
pwrmgr_csr_rw 0.690s 42.139us 1 1 100.00
pwrmgr_csr_aliasing 0.850s 113.983us 1 1 100.00
pwrmgr_same_csr_outstanding 0.790s 84.393us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
pwrmgr_tl_intg_err 1.190s 1493.405us 1 1 100.00
pwrmgr_sec_cm 1.020s 393.014us 1 1 100.00
prim_count_check 1 1 100.00
pwrmgr_sec_cm 1.020s 393.014us 1 1 100.00
prim_fsm_check 1 1 100.00
pwrmgr_sec_cm 1.020s 393.014us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
pwrmgr_tl_intg_err 1.190s 1493.405us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_lc_ctrl_intersig_mubi 1.820s 835.282us 1 1 100.00
sec_cm_rom_ctrl_intersig_mubi 2 2 100.00
pwrmgr_wakeup_reset 0.830s 153.134us 1 1 100.00
pwrmgr_repeat_wakeup_reset 1.530s 1823.853us 1 1 100.00
sec_cm_rstmgr_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_rstmgr_intersig_mubi 0.780s 347.163us 1 1 100.00
sec_cm_esc_rx_clk_bkgn_chk 1 1 100.00
pwrmgr_esc_clk_rst_malfunc 0.570s 100.847us 1 1 100.00
sec_cm_esc_rx_clk_local_esc 1 1 100.00
pwrmgr_sec_cm 1.020s 393.014us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
pwrmgr_sec_cm 1.020s 393.014us 1 1 100.00
sec_cm_fsm_terminal 1 1 100.00
pwrmgr_sec_cm 1.020s 393.014us 1 1 100.00
sec_cm_ctrl_flow_global_esc 1 1 100.00
pwrmgr_global_esc 0.610s 73.442us 1 1 100.00
sec_cm_main_pd_rst_local_esc 1 1 100.00
pwrmgr_glitch 0.570s 49.438us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
pwrmgr_sec_cm_ctrl_config_regwen 0.820s 204.585us 1 1 100.00
sec_cm_wakeup_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.690s 42.139us 1 1 100.00
sec_cm_reset_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.690s 42.139us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
escalation_timeout 1 1 100.00
pwrmgr_escalation_timeout 0.800s 106.000us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
pwrmgr_stress_all_with_rand_reset 5.000s 2185.028us 1 1 100.00