Simulation Results: rom_ctrl/32kb

 
10/08/2026 15:30:36 DVSim: v1.50.1 sha: af43bb2 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 93.92 %
  • code
  • 88.10 %
  • assert
  • 97.53 %
  • func
  • 96.14 %
  • line
  • 98.53 %
  • branch
  • 98.54 %
  • cond
  • 95.84 %
  • toggle
  • 94.24 %
  • FSM
  • 53.33 %
Validation stages
V1
100.00%
V2
88.89%
V2S
83.33%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 2.990s 777.601us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 2.750s 57.642us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 1.820s 54.774us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 2.080s 61.458us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 1.870s 55.802us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 1.940s 61.918us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 1.820s 54.774us 1 1 100.00
rom_ctrl_csr_aliasing 1.870s 55.802us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 1.700s 86.457us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 1.690s 92.525us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 0 1 0.00
rom_ctrl_max_throughput_chk 1.750s 8.506us 0 1 0.00
stress_all 1 1 100.00
rom_ctrl_stress_all 8.630s 1102.254us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 2.780s 62.358us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 1.830s 51.834us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 4.180s 357.822us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 4.180s 357.822us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 2.750s 57.642us 1 1 100.00
rom_ctrl_csr_rw 1.820s 54.774us 1 1 100.00
rom_ctrl_csr_aliasing 1.870s 55.802us 1 1 100.00
rom_ctrl_same_csr_outstanding 1.970s 64.284us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 2.750s 57.642us 1 1 100.00
rom_ctrl_csr_rw 1.820s 54.774us 1 1 100.00
rom_ctrl_csr_aliasing 1.870s 55.802us 1 1 100.00
rom_ctrl_same_csr_outstanding 1.970s 64.284us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.120s 0.000us 0 1 0.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 7.120s 195.572us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 105.710s 1413.627us 1 1 100.00
rom_ctrl_tl_intg_err 23.410s 346.329us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 105.710s 1413.627us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 105.710s 1413.627us 1 1 100.00
sec_cm_checker_ctr_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.120s 0.000us 0 1 0.00
sec_cm_checker_ctrl_flow_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.120s 0.000us 0 1 0.00
sec_cm_checker_fsm_local_esc 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.120s 0.000us 0 1 0.00
sec_cm_compare_ctrl_flow_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.120s 0.000us 0 1 0.00
sec_cm_compare_ctr_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.120s 0.000us 0 1 0.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 105.710s 1413.627us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 105.710s 1413.627us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 2.990s 777.601us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 2.990s 777.601us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 2.990s 777.601us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 23.410s 346.329us 1 1 100.00
sec_cm_bus_local_esc 1 2 50.00
rom_ctrl_corrupt_sig_fatal_chk 3600.120s 0.000us 0 1 0.00
rom_ctrl_kmac_err_chk 2.780s 62.358us 1 1 100.00
sec_cm_mux_mubi 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.120s 0.000us 0 1 0.00
sec_cm_mux_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.120s 0.000us 0 1 0.00
sec_cm_ctrl_redun 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.120s 0.000us 0 1 0.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 7.120s 195.572us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 105.710s 1413.627us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 43.990s 2177.339us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (rom_ctrl_throughput_vseq.sv:52) [rom_ctrl_throughput_vseq] Check failed num_cycles == num_mem_reads + * (* [*] vs * [*]) 1 test run
rom_ctrl_max_throughput_chk 8367202269369322815777309230638284579699052992796192132145403572190676473336 79
UVM_INFO @ 8505832 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes 1 test run
rom_ctrl_corrupt_sig_fatal_chk 78599178828277061545756136769989478331349426305693482500186591955171274859463 None