Simulation Results: rom_ctrl/64kb

 
10/08/2026 15:30:36 DVSim: v1.50.1 sha: af43bb2 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 94.20 %
  • code
  • 89.81 %
  • assert
  • 96.66 %
  • func
  • 96.14 %
  • line
  • 98.66 %
  • branch
  • 98.91 %
  • cond
  • 96.14 %
  • toggle
  • 95.34 %
  • FSM
  • 60.00 %
Validation stages
V1
100.00%
V2
88.89%
V2S
83.33%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 6.510s 1400.007us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 5.480s 58.884us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 3.190s 92.499us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 3.280s 61.134us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 4.120s 87.501us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 3.950s 121.977us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 3.190s 92.499us 1 1 100.00
rom_ctrl_csr_aliasing 4.120s 87.501us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 3.190s 75.776us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 3.190s 49.937us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 0 1 0.00
rom_ctrl_max_throughput_chk 2.880s 8.753us 0 1 0.00
stress_all 1 1 100.00
rom_ctrl_stress_all 17.820s 4081.355us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 10.390s 5100.538us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 3.500s 52.274us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 9.030s 706.434us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 9.030s 706.434us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 5.480s 58.884us 1 1 100.00
rom_ctrl_csr_rw 3.190s 92.499us 1 1 100.00
rom_ctrl_csr_aliasing 4.120s 87.501us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.660s 95.282us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 5.480s 58.884us 1 1 100.00
rom_ctrl_csr_rw 3.190s 92.499us 1 1 100.00
rom_ctrl_csr_aliasing 4.120s 87.501us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.660s 95.282us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.107s 0.000us 0 1 0.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 9.880s 160.975us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 242.870s 711.621us 1 1 100.00
rom_ctrl_tl_intg_err 97.160s 400.060us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 242.870s 711.621us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 242.870s 711.621us 1 1 100.00
sec_cm_checker_ctr_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.107s 0.000us 0 1 0.00
sec_cm_checker_ctrl_flow_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.107s 0.000us 0 1 0.00
sec_cm_checker_fsm_local_esc 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.107s 0.000us 0 1 0.00
sec_cm_compare_ctrl_flow_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.107s 0.000us 0 1 0.00
sec_cm_compare_ctr_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.107s 0.000us 0 1 0.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 242.870s 711.621us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 242.870s 711.621us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 6.510s 1400.007us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 6.510s 1400.007us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 6.510s 1400.007us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 97.160s 400.060us 1 1 100.00
sec_cm_bus_local_esc 1 2 50.00
rom_ctrl_corrupt_sig_fatal_chk 3600.107s 0.000us 0 1 0.00
rom_ctrl_kmac_err_chk 10.390s 5100.538us 1 1 100.00
sec_cm_mux_mubi 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.107s 0.000us 0 1 0.00
sec_cm_mux_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.107s 0.000us 0 1 0.00
sec_cm_ctrl_redun 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.107s 0.000us 0 1 0.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 9.880s 160.975us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 242.870s 711.621us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 67.130s 3852.736us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (rom_ctrl_throughput_vseq.sv:52) [rom_ctrl_throughput_vseq] Check failed num_cycles == num_mem_reads + * (* [*] vs * [*]) 1 test run
rom_ctrl_max_throughput_chk 876578951332981309201499590027879546067934917537752156205327243195381899040 79
UVM_INFO @ 8752657 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes 1 test run
rom_ctrl_corrupt_sig_fatal_chk 43672112569324033272999242320891453673796384755804872591781371094788250220360 None