Simulation Results: rstmgr

 
10/08/2026 15:30:36 DVSim: v1.50.1 sha: af43bb2 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.60 %
  • code
  • 99.39 %
  • assert
  • 98.66 %
  • func
  • 97.76 %
  • line
  • 99.51 %
  • branch
  • 99.83 %
  • cond
  • 98.96 %
  • toggle
  • 99.25 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rstmgr_smoke 1.790s 296.493us 1 1 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 0.970s 93.236us 1 1 100.00
csr_rw 1 1 100.00
rstmgr_csr_rw 0.840s 76.022us 1 1 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 7.860s 2857.016us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 1.170s 109.531us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rstmgr_csr_mem_rw_with_rand_reset 0.860s 119.949us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rstmgr_csr_rw 0.840s 76.022us 1 1 100.00
rstmgr_csr_aliasing 1.170s 109.531us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 1 1 100.00
rstmgr_por_stretcher 0.830s 145.068us 1 1 100.00
sw_rst 1 1 100.00
rstmgr_sw_rst 1.590s 191.031us 1 1 100.00
sw_rst_reset_race 1 1 100.00
rstmgr_sw_rst_reset_race 1.000s 137.244us 1 1 100.00
reset_info 1 1 100.00
rstmgr_reset 5.040s 1854.039us 1 1 100.00
cpu_info 1 1 100.00
rstmgr_reset 5.040s 1854.039us 1 1 100.00
alert_info 1 1 100.00
rstmgr_reset 5.040s 1854.039us 1 1 100.00
reset_info_capture 1 1 100.00
rstmgr_reset 5.040s 1854.039us 1 1 100.00
stress_all 1 1 100.00
rstmgr_stress_all 13.570s 4771.524us 1 1 100.00
alert_test 1 1 100.00
rstmgr_alert_test 0.800s 99.364us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rstmgr_tl_errors 1.790s 163.905us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rstmgr_tl_errors 1.790s 163.905us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rstmgr_csr_hw_reset 0.970s 93.236us 1 1 100.00
rstmgr_csr_rw 0.840s 76.022us 1 1 100.00
rstmgr_csr_aliasing 1.170s 109.531us 1 1 100.00
rstmgr_same_csr_outstanding 1.060s 136.481us 1 1 100.00
tl_d_partial_access 4 4 100.00
rstmgr_csr_hw_reset 0.970s 93.236us 1 1 100.00
rstmgr_csr_rw 0.840s 76.022us 1 1 100.00
rstmgr_csr_aliasing 1.170s 109.531us 1 1 100.00
rstmgr_same_csr_outstanding 1.060s 136.481us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rstmgr_sec_cm 10.740s 8518.631us 1 1 100.00
rstmgr_tl_intg_err 2.520s 934.788us 1 1 100.00
prim_count_check 1 1 100.00
rstmgr_sec_cm 10.740s 8518.631us 1 1 100.00
prim_fsm_check 1 1 100.00
rstmgr_sec_cm 10.740s 8518.631us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rstmgr_tl_intg_err 2.520s 934.788us 1 1 100.00
sec_cm_scan_intersig_mubi 1 1 100.00
rstmgr_sec_cm_scan_intersig_mubi 0.870s 118.314us 1 1 100.00
sec_cm_leaf_rst_bkgn_chk 1 1 100.00
rstmgr_leaf_rst_cnsty 6.260s 2587.100us 1 1 100.00
sec_cm_leaf_rst_shadow 1 1 100.00
rstmgr_leaf_rst_shadow_attack 1.350s 303.149us 1 1 100.00
sec_cm_leaf_fsm_sparse 1 1 100.00
rstmgr_sec_cm 10.740s 8518.631us 1 1 100.00
sec_cm_sw_rst_config_regwen 1 1 100.00
rstmgr_csr_rw 0.840s 76.022us 1 1 100.00
sec_cm_dump_ctrl_config_regwen 1 1 100.00
rstmgr_csr_rw 0.840s 76.022us 1 1 100.00