Simulation Results: rv_timer

 
10/08/2026 15:30:36 DVSim: v1.50.1 sha: af43bb2 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 93.25 %
  • code
  • 94.56 %
  • assert
  • 98.73 %
  • func
  • 86.47 %
  • line
  • 100.00 %
  • branch
  • 100.00 %
  • cond
  • 100.00 %
  • toggle
  • 78.25 %
Validation stages
V1
100.00%
V2
90.91%
V2S
100.00%
V3
33.33%
Testpoint Test Max Runtime Sim Time Pass Total %
random 1 1 100.00
rv_timer_random 0.770s 170.908us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 0.570s 14.720us 1 1 100.00
csr_rw 1 1 100.00
rv_timer_csr_rw 0.690s 51.563us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 1.190s 267.617us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 1.020s 37.160us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_timer_csr_mem_rw_with_rand_reset 0.690s 135.268us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_timer_csr_rw 0.690s 51.563us 1 1 100.00
rv_timer_csr_aliasing 1.020s 37.160us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 0 1 0.00
rv_timer_random_reset 1.230s 1569.614us 0 1 0.00
disabled 1 1 100.00
rv_timer_disabled 0.830s 136.666us 1 1 100.00
cfg_update_on_fly 1 1 100.00
rv_timer_cfg_update_on_fly 196.670s 1092011.761us 1 1 100.00
no_interrupt_test 1 1 100.00
rv_timer_cfg_update_on_fly 196.670s 1092011.761us 1 1 100.00
stress 1 1 100.00
rv_timer_stress_all 1.550s 2122.866us 1 1 100.00
alert_test 1 1 100.00
rv_timer_alert_test 0.730s 124.019us 1 1 100.00
intr_test 1 1 100.00
rv_timer_intr_test 0.610s 33.432us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_timer_tl_errors 2.100s 545.425us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_timer_tl_errors 2.100s 545.425us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_timer_csr_hw_reset 0.570s 14.720us 1 1 100.00
rv_timer_csr_rw 0.690s 51.563us 1 1 100.00
rv_timer_csr_aliasing 1.020s 37.160us 1 1 100.00
rv_timer_same_csr_outstanding 0.880s 374.795us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_timer_csr_hw_reset 0.570s 14.720us 1 1 100.00
rv_timer_csr_rw 0.690s 51.563us 1 1 100.00
rv_timer_csr_aliasing 1.020s 37.160us 1 1 100.00
rv_timer_same_csr_outstanding 0.880s 374.795us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_timer_sec_cm 0.870s 90.139us 1 1 100.00
rv_timer_tl_intg_err 1.600s 128.191us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_timer_tl_intg_err 1.600s 128.191us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 0 1 0.00
rv_timer_min 0.690s 60.429us 0 1 0.00
max_value 0 1 0.00
rv_timer_max 0.760s 269.421us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
rv_timer_stress_all_with_rand_reset 14.130s 2314.677us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * 2 test runs
rv_timer_min 19582017750926735808969161350454820998918509861874175387189431262895453845629 75
UVM_INFO @ 60429442 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 97453781753667980320636915379908039159937483218121779645716308099151483699531 75
UVM_INFO @ 1569614358 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) 1 test run
rv_timer_max 77368069925117887762866809720814888543757057214887900606443608422805745845361 75
UVM_INFO @ 269420503 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---