Simulation Results: sram_ctrl/main

 
10/08/2026 15:30:36 DVSim: v1.50.1 sha: af43bb2 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 95.55 %
  • code
  • 94.63 %
  • assert
  • 97.82 %
  • func
  • 94.20 %
  • block
  • 94.68 %
  • line
  • 95.12 %
  • branch
  • 91.56 %
  • toggle
  • 91.84 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 4.000s 1545.331us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 13.708us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 1.000s 48.558us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 3.000s 521.602us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 189.824us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 5.000s 1485.509us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 1.000s 48.558us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 189.824us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 89.000s 3118.654us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 47.000s 10374.139us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 15.000s 14634.715us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 75.000s 9236.394us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 157.000s 18422.545us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 43.000s 11805.317us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 26.000s 10183.277us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 24.000s 5452.310us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 5.000s 2761.175us 1 1 100.00
sram_ctrl_partial_access_b2b 238.000s 38995.507us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 4.000s 2900.245us 1 1 100.00
sram_ctrl_throughput_w_partial_write 5.000s 668.228us 1 1 100.00
sram_ctrl_throughput_w_readback 3.000s 13197.214us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 7.000s 887.992us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 3.000s 691.192us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 64.000s 16140.901us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 2.000s 27.583us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 1.000s 23.667us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 1.000s 23.667us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 13.708us 1 1 100.00
sram_ctrl_csr_rw 1.000s 48.558us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 189.824us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 25.423us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 13.708us 1 1 100.00
sram_ctrl_csr_rw 1.000s 48.558us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 189.824us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 25.423us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 20.000s 30713.212us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 3.000s 607.565us 1 1 100.00
sram_ctrl_tl_intg_err 1.000s 97.935us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 3.000s 607.565us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 1.000s 97.935us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 7.000s 887.992us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 7.000s 887.992us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 1.000s 48.558us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 24.000s 5452.310us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 24.000s 5452.310us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 24.000s 5452.310us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 26.000s 10183.277us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 6.000s 3038.939us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 20.000s 30713.212us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 4.000s 5146.722us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 4.000s 1545.331us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 4.000s 1545.331us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 24.000s 5452.310us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 3.000s 607.565us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 26.000s 10183.277us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 3.000s 607.565us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 607.565us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 4.000s 1545.331us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 607.565us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 4.000s 695.700us 1 1 100.00