Simulation Results: sram_ctrl/ret

 
10/08/2026 15:30:36 DVSim: v1.50.1 sha: af43bb2 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 91.51 %
  • code
  • 82.12 %
  • assert
  • 97.81 %
  • func
  • 94.60 %
  • block
  • 93.47 %
  • line
  • 94.53 %
  • branch
  • 89.01 %
  • toggle
  • 78.28 %
  • FSM
  • 66.67 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 1.000s 58.088us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 31.551us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 1.000s 23.276us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 1.000s 63.870us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 35.618us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 3.000s 34.727us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 1.000s 23.276us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 35.618us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 9.000s 2983.104us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 4.000s 624.104us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 8.000s 1069.489us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 111.000s 2377.628us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 8.000s 2923.030us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 9.000s 1303.696us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 5.000s 592.636us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 7.000s 386.536us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 3.000s 232.906us 1 1 100.00
sram_ctrl_partial_access_b2b 292.000s 95889.893us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 2.000s 71.521us 1 1 100.00
sram_ctrl_throughput_w_partial_write 1.000s 71.437us 1 1 100.00
sram_ctrl_throughput_w_readback 2.000s 46.548us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 3.000s 396.657us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 2.000s 31.288us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 26.000s 3143.360us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 1.000s 52.540us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 3.000s 31.474us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 3.000s 31.474us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 31.551us 1 1 100.00
sram_ctrl_csr_rw 1.000s 23.276us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 35.618us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 44.741us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 31.551us 1 1 100.00
sram_ctrl_csr_rw 1.000s 23.276us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 35.618us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 44.741us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 2.000s 313.475us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 3.000s 2432.405us 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 378.174us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 3.000s 2432.405us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 378.174us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 3.000s 396.657us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 3.000s 396.657us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 1.000s 23.276us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 7.000s 386.536us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 7.000s 386.536us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 7.000s 386.536us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 5.000s 592.636us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 1.000s 147.677us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 2.000s 313.475us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 1.000s 81.491us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 1.000s 58.088us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 1.000s 58.088us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 7.000s 386.536us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 3.000s 2432.405us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 5.000s 592.636us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 3.000s 2432.405us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 2432.405us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 1.000s 58.088us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 2432.405us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 32.000s 3930.541us 1 1 100.00