Simulation Results: sysrst_ctrl

 
10/08/2026 15:30:36 DVSim: v1.50.1 sha: af43bb2 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 83.00 %
  • code
  • 92.76 %
  • assert
  • 94.35 %
  • func
  • 61.90 %
  • line
  • 97.26 %
  • branch
  • 97.48 %
  • cond
  • 94.72 %
  • toggle
  • 100.00 %
  • FSM
  • 74.36 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sysrst_ctrl_smoke 1.530s 2135.243us 1 1 100.00
input_output_inverted 1 1 100.00
sysrst_ctrl_in_out_inverted 2.120s 2482.319us 1 1 100.00
combo_detect_ec_rst 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst 1.440s 2285.544us 1 1 100.00
combo_detect_ec_rst_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 1.990s 2522.393us 1 1 100.00
csr_hw_reset 1 1 100.00
sysrst_ctrl_csr_hw_reset 3.810s 6089.230us 1 1 100.00
csr_rw 1 1 100.00
sysrst_ctrl_csr_rw 1.640s 2127.677us 1 1 100.00
csr_bit_bash 1 1 100.00
sysrst_ctrl_csr_bit_bash 11.580s 17965.464us 1 1 100.00
csr_aliasing 1 1 100.00
sysrst_ctrl_csr_aliasing 5.360s 3150.766us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sysrst_ctrl_csr_mem_rw_with_rand_reset 4.220s 2090.765us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sysrst_ctrl_csr_rw 1.640s 2127.677us 1 1 100.00
sysrst_ctrl_csr_aliasing 5.360s 3150.766us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
combo_detect 1 1 100.00
sysrst_ctrl_combo_detect 47.660s 108679.206us 1 1 100.00
combo_detect_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_with_pre_cond 92.150s 50515.865us 1 1 100.00
auto_block_key_outputs 1 1 100.00
sysrst_ctrl_auto_blk_key_output 6.550s 3774.478us 1 1 100.00
keyboard_input_triggered_interrupt 1 1 100.00
sysrst_ctrl_edge_detect 2.630s 4893.735us 1 1 100.00
pin_output_keyboard_inversion_control 1 1 100.00
sysrst_ctrl_pin_override_test 5.250s 2515.582us 1 1 100.00
pin_input_value_accessibility 1 1 100.00
sysrst_ctrl_pin_access_test 1.340s 2131.267us 1 1 100.00
ec_power_on_reset 1 1 100.00
sysrst_ctrl_ec_pwr_on_rst 1469.420s 1027277.622us 1 1 100.00
flash_write_protect_output 1 1 100.00
sysrst_ctrl_flash_wr_prot_out 1.540s 2674.145us 1 1 100.00
ultra_low_power_test 1 1 100.00
sysrst_ctrl_ultra_low_pwr 4.570s 4876.120us 1 1 100.00
sysrst_ctrl_feature_disable 1 1 100.00
sysrst_ctrl_feature_disable 30.160s 38076.382us 1 1 100.00
stress_all 1 1 100.00
sysrst_ctrl_stress_all 23.340s 14827.605us 1 1 100.00
alert_test 1 1 100.00
sysrst_ctrl_alert_test 3.770s 2015.099us 1 1 100.00
intr_test 1 1 100.00
sysrst_ctrl_intr_test 2.190s 2030.470us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sysrst_ctrl_tl_errors 1.850s 2278.124us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sysrst_ctrl_tl_errors 1.850s 2278.124us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 3.810s 6089.230us 1 1 100.00
sysrst_ctrl_csr_rw 1.640s 2127.677us 1 1 100.00
sysrst_ctrl_csr_aliasing 5.360s 3150.766us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 2.840s 8061.709us 1 1 100.00
tl_d_partial_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 3.810s 6089.230us 1 1 100.00
sysrst_ctrl_csr_rw 1.640s 2127.677us 1 1 100.00
sysrst_ctrl_csr_aliasing 5.360s 3150.766us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 2.840s 8061.709us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
sysrst_ctrl_sec_cm 36.080s 42041.876us 1 1 100.00
sysrst_ctrl_tl_intg_err 10.760s 22346.027us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sysrst_ctrl_tl_intg_err 10.760s 22346.027us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sysrst_ctrl_stress_all_with_rand_reset 5.720s 10178.167us 1 1 100.00