Simulation Results: uart

 
10/08/2026 15:30:36 DVSim: v1.50.1 sha: af43bb2 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 83.00 %
  • code
  • 91.65 %
  • assert
  • 98.85 %
  • func
  • 58.49 %
  • line
  • 99.17 %
  • branch
  • 97.44 %
  • cond
  • 95.33 %
  • toggle
  • 74.67 %
Validation stages
V1
100.00%
V2
95.45%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
uart_smoke 2.330s 289.224us 1 1 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 0.780s 21.064us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 0.730s 49.129us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 2.300s 634.224us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 0.910s 55.285us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 0.670s 24.798us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 0.730s 49.129us 1 1 100.00
uart_csr_aliasing 0.910s 55.285us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 1 1 100.00
uart_tx_rx 11.990s 182887.118us 1 1 100.00
parity 2 2 100.00
uart_smoke 2.330s 289.224us 1 1 100.00
uart_tx_rx 11.990s 182887.118us 1 1 100.00
parity_error 2 2 100.00
uart_intr 34.410s 46558.190us 1 1 100.00
uart_rx_parity_err 61.240s 140167.639us 1 1 100.00
watermark 2 2 100.00
uart_tx_rx 11.990s 182887.118us 1 1 100.00
uart_intr 34.410s 46558.190us 1 1 100.00
fifo_full 1 1 100.00
uart_fifo_full 30.160s 52068.300us 1 1 100.00
fifo_overflow 1 1 100.00
uart_fifo_overflow 40.510s 31238.606us 1 1 100.00
fifo_reset 1 1 100.00
uart_fifo_reset 17.680s 42299.250us 1 1 100.00
rx_frame_err 1 1 100.00
uart_intr 34.410s 46558.190us 1 1 100.00
rx_break_err 1 1 100.00
uart_intr 34.410s 46558.190us 1 1 100.00
rx_timeout 1 1 100.00
uart_intr 34.410s 46558.190us 1 1 100.00
perf 1 1 100.00
uart_perf 424.980s 18089.716us 1 1 100.00
sys_loopback 1 1 100.00
uart_loopback 4.760s 10077.094us 1 1 100.00
line_loopback 1 1 100.00
uart_loopback 4.760s 10077.094us 1 1 100.00
rx_noise_filter 0 1 0.00
uart_noise_filter 1.590s 1754.863us 0 1 0.00
rx_start_bit_filter 1 1 100.00
uart_rx_start_bit_filter 29.500s 35931.043us 1 1 100.00
tx_overide 1 1 100.00
uart_tx_ovrd 14.610s 6110.382us 1 1 100.00
rx_oversample 1 1 100.00
uart_rx_oversample 14.470s 3888.623us 1 1 100.00
long_b2b_transfer 1 1 100.00
uart_long_xfer_wo_dly 157.910s 68926.341us 1 1 100.00
stress_all 1 1 100.00
uart_stress_all 103.810s 177310.245us 1 1 100.00
alert_test 1 1 100.00
uart_alert_test 0.630s 37.358us 1 1 100.00
intr_test 1 1 100.00
uart_intr_test 0.670s 55.628us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 1.770s 82.514us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 1.770s 82.514us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 0.780s 21.064us 1 1 100.00
uart_csr_rw 0.730s 49.129us 1 1 100.00
uart_csr_aliasing 0.910s 55.285us 1 1 100.00
uart_same_csr_outstanding 0.750s 73.270us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 0.780s 21.064us 1 1 100.00
uart_csr_rw 0.730s 49.129us 1 1 100.00
uart_csr_aliasing 0.910s 55.285us 1 1 100.00
uart_same_csr_outstanding 0.750s 73.270us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
uart_sec_cm 0.870s 142.291us 1 1 100.00
uart_tl_intg_err 1.190s 192.343us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 1.190s 192.343us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
uart_stress_all_with_rand_reset 18.310s 10507.235us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uart_scoreboard.sv:393) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [*] vs * [*]) check rx_idle fail: rx_en = *, uart_rx_clk_pulses = * 1 test run
uart_noise_filter 102127382074598619070260007148289100400243231760089498395430683103016040886168 75
UVM_ERROR @ 682311761 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 942084109 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
UVM_ERROR @ 942084109 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 951507299 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0