Simulation Results: adc_ctrl

 
11/08/2026 15:30:30 DVSim: v1.50.1 sha: 14c137f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 70.38 %
  • code
  • 95.72 %
  • assert
  • 96.92 %
  • func
  • 18.49 %
  • line
  • 99.02 %
  • branch
  • 98.45 %
  • cond
  • 94.62 %
  • toggle
  • 100.00 %
  • FSM
  • 86.49 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
adc_ctrl_smoke 4.780s 5996.210us 1 1 100.00
csr_hw_reset 1 1 100.00
adc_ctrl_csr_hw_reset 2.420s 1279.761us 1 1 100.00
csr_rw 1 1 100.00
adc_ctrl_csr_rw 0.800s 572.086us 1 1 100.00
csr_bit_bash 1 1 100.00
adc_ctrl_csr_bit_bash 11.140s 10040.103us 1 1 100.00
csr_aliasing 1 1 100.00
adc_ctrl_csr_aliasing 1.280s 1318.096us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
adc_ctrl_csr_mem_rw_with_rand_reset 0.910s 581.118us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
adc_ctrl_csr_rw 0.800s 572.086us 1 1 100.00
adc_ctrl_csr_aliasing 1.280s 1318.096us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
filters_polled 1 1 100.00
adc_ctrl_filters_polled 42.830s 37146.529us 1 1 100.00
filters_polled_fixed 1 1 100.00
adc_ctrl_filters_polled_fixed 22.330s 54220.208us 1 1 100.00
filters_interrupt 1 1 100.00
adc_ctrl_filters_interrupt 5.890s 19429.550us 1 1 100.00
filters_interrupt_fixed 1 1 100.00
adc_ctrl_filters_interrupt_fixed 3.230s 19055.329us 1 1 100.00
filters_wakeup 1 1 100.00
adc_ctrl_filters_wakeup 64.430s 50091.308us 1 1 100.00
filters_wakeup_fixed 1 1 100.00
adc_ctrl_filters_wakeup_fixed 49.740s 73413.982us 1 1 100.00
filters_both 1 1 100.00
adc_ctrl_filters_both 15.190s 62002.148us 1 1 100.00
clock_gating 1 1 100.00
adc_ctrl_clock_gating 3.200s 22321.334us 1 1 100.00
poweron_counter 1 1 100.00
adc_ctrl_poweron_counter 6.130s 4200.069us 1 1 100.00
lowpower_counter 1 1 100.00
adc_ctrl_lowpower_counter 47.800s 44921.920us 1 1 100.00
fsm_reset 1 1 100.00
adc_ctrl_fsm_reset 124.970s 93090.605us 1 1 100.00
stress_all 1 1 100.00
adc_ctrl_stress_all 56.550s 40653.259us 1 1 100.00
alert_test 1 1 100.00
adc_ctrl_alert_test 0.820s 467.669us 1 1 100.00
intr_test 1 1 100.00
adc_ctrl_intr_test 1.020s 501.752us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
adc_ctrl_tl_errors 2.130s 1103.897us 1 1 100.00
tl_d_illegal_access 1 1 100.00
adc_ctrl_tl_errors 2.130s 1103.897us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
adc_ctrl_csr_hw_reset 2.420s 1279.761us 1 1 100.00
adc_ctrl_csr_rw 0.800s 572.086us 1 1 100.00
adc_ctrl_csr_aliasing 1.280s 1318.096us 1 1 100.00
adc_ctrl_same_csr_outstanding 6.420s 4140.678us 1 1 100.00
tl_d_partial_access 4 4 100.00
adc_ctrl_csr_hw_reset 2.420s 1279.761us 1 1 100.00
adc_ctrl_csr_rw 0.800s 572.086us 1 1 100.00
adc_ctrl_csr_aliasing 1.280s 1318.096us 1 1 100.00
adc_ctrl_same_csr_outstanding 6.420s 4140.678us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
adc_ctrl_sec_cm 6.940s 4220.713us 1 1 100.00
adc_ctrl_tl_intg_err 13.200s 8382.576us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
adc_ctrl_tl_intg_err 13.200s 8382.576us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
adc_ctrl_stress_all_with_rand_reset 6.660s 3443.245us 1 1 100.00