Simulation Results: chip

 
11/08/2026 15:30:30 DVSim: v1.50.1 sha: 14c137f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 76.89 %
  • code
  • 81.74 %
  • assert
  • 97.62 %
  • func
  • 51.31 %
  • line
  • 94.40 %
  • branch
  • 94.13 %
  • cond
  • 89.30 %
  • toggle
  • 73.71 %
  • FSM
  • 57.14 %
Validation stages
V1
94.44%
V2
89.17%
V2S
50.00%
V3
65.38%
unmapped
63.64%
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_example_tests 4 4 100.00
chip_sw_example_flash 210.990s 2753.058us 1 1 100.00
chip_sw_example_rom 91.990s 2851.906us 1 1 100.00
chip_sw_example_manufacturer 229.330s 3174.142us 1 1 100.00
chip_sw_example_concurrency 181.710s 3893.675us 1 1 100.00
csr_hw_reset 1 1 100.00
chip_csr_hw_reset 175.400s 4703.361us 1 1 100.00
csr_rw 1 1 100.00
chip_csr_rw 500.430s 6963.483us 1 1 100.00
csr_bit_bash 1 1 100.00
chip_csr_bit_bash 289.090s 4806.546us 1 1 100.00
csr_aliasing 1 1 100.00
chip_csr_aliasing 5680.560s 38413.604us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
chip_csr_mem_rw_with_rand_reset 82.400s 2427.554us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
chip_csr_aliasing 5680.560s 38413.604us 1 1 100.00
chip_csr_rw 500.430s 6963.483us 1 1 100.00
xbar_smoke 1 1 100.00
xbar_smoke 4.700s 41.510us 1 1 100.00
chip_sw_gpio_out 1 1 100.00
chip_sw_gpio 332.310s 4342.082us 1 1 100.00
chip_sw_gpio_in 1 1 100.00
chip_sw_gpio 332.310s 4342.082us 1 1 100.00
chip_sw_gpio_irq 1 1 100.00
chip_sw_gpio 332.310s 4342.082us 1 1 100.00
chip_sw_uart_tx_rx 1 1 100.00
chip_sw_uart_tx_rx 403.420s 5040.904us 1 1 100.00
chip_sw_uart_rx_overflow 4 4 100.00
chip_sw_uart_tx_rx 403.420s 5040.904us 1 1 100.00
chip_sw_uart_tx_rx_idx1 435.980s 5453.388us 1 1 100.00
chip_sw_uart_tx_rx_idx2 405.990s 5254.978us 1 1 100.00
chip_sw_uart_tx_rx_idx3 404.760s 5164.180us 1 1 100.00
chip_sw_uart_baud_rate 1 1 100.00
chip_sw_uart_rand_baudrate 1036.200s 8654.647us 1 1 100.00
chip_sw_uart_tx_rx_alt_clk_freq 2 2 100.00
chip_sw_uart_tx_rx_alt_clk_freq 1157.350s 8826.022us 1 1 100.00
chip_sw_uart_tx_rx_alt_clk_freq_low_speed 390.470s 5377.997us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_pin_mux 1 1 100.00
chip_padctrl_attributes 223.590s 6199.331us 1 1 100.00
chip_padctrl_attributes 1 1 100.00
chip_padctrl_attributes 223.590s 6199.331us 1 1 100.00
chip_sw_sleep_pin_mio_dio_val 1 1 100.00
chip_sw_sleep_pin_mio_dio_val 241.140s 4103.911us 1 1 100.00
chip_sw_sleep_pin_wake 0 1 0.00
chip_sw_sleep_pin_wake 192.600s 3575.269us 0 1 0.00
chip_sw_sleep_pin_retention 1 1 100.00
chip_sw_sleep_pin_retention 249.680s 4986.402us 1 1 100.00
chip_sw_tap_strap_sampling 4 4 100.00
chip_tap_straps_dev 109.000s 2974.299us 1 1 100.00
chip_tap_straps_testunlock0 309.050s 5647.014us 1 1 100.00
chip_tap_straps_rma 527.440s 8431.211us 1 1 100.00
chip_tap_straps_prod 142.630s 3497.886us 1 1 100.00
chip_sw_data_integrity 1 1 100.00
chip_sw_data_integrity_escalation 611.290s 7229.522us 1 1 100.00
chip_sw_instruction_integrity 1 1 100.00
chip_sw_data_integrity_escalation 611.290s 7229.522us 1 1 100.00
chip_sw_ast_clk_outputs 1 1 100.00
chip_sw_ast_clk_outputs 704.720s 8136.352us 1 1 100.00
chip_sw_ast_clk_rst_inputs 0 1 0.00
chip_sw_ast_clk_rst_inputs 2000.790s 16486.212us 0 1 0.00
chip_sw_ast_sys_clk_jitter 10 10 100.00
chip_sw_flash_ctrl_ops_jitter_en 386.160s 4555.695us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 649.620s 5753.124us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 4395.020s 18971.013us 1 1 100.00
chip_sw_aes_enc_jitter_en 183.730s 3190.203us 1 1 100.00
chip_sw_edn_entropy_reqs_jitter 823.600s 7278.690us 1 1 100.00
chip_sw_hmac_enc_jitter_en 182.840s 3522.075us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 1354.290s 10008.567us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 230.950s 4449.610us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 529.180s 6794.124us 1 1 100.00
chip_sw_clkmgr_jitter 233.090s 3784.203us 1 1 100.00
chip_sw_ast_usb_clk_calib 1 1 100.00
chip_sw_usb_ast_clk_calib 237.050s 3525.925us 1 1 100.00
chip_sw_sensor_ctrl_ast_alerts 2 2 100.00
chip_sw_sensor_ctrl_alert 780.150s 8530.152us 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 360.250s 6166.711us 1 1 100.00
chip_sw_sensor_ctrl_ast_status 1 1 100.00
chip_sw_sensor_ctrl_status 219.130s 3943.690us 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 360.250s 6166.711us 1 1 100.00
chip_sw_smoketest 17 17 100.00
chip_sw_flash_scrambling_smoketest 214.250s 3242.732us 1 1 100.00
chip_sw_aes_smoketest 198.460s 3516.859us 1 1 100.00
chip_sw_aon_timer_smoketest 234.580s 4067.473us 1 1 100.00
chip_sw_clkmgr_smoketest 219.740s 3774.908us 1 1 100.00
chip_sw_csrng_smoketest 218.940s 3301.151us 1 1 100.00
chip_sw_entropy_src_smoketest 986.260s 7220.615us 1 1 100.00
chip_sw_gpio_smoketest 260.420s 3936.207us 1 1 100.00
chip_sw_hmac_smoketest 251.410s 3325.332us 1 1 100.00
chip_sw_kmac_smoketest 209.390s 3804.358us 1 1 100.00
chip_sw_otbn_smoketest 1155.780s 8774.523us 1 1 100.00
chip_sw_pwrmgr_smoketest 470.830s 7806.374us 1 1 100.00
chip_sw_pwrmgr_usbdev_smoketest 336.260s 7598.341us 1 1 100.00
chip_sw_rv_plic_smoketest 183.490s 3066.568us 1 1 100.00
chip_sw_rv_timer_smoketest 218.850s 4685.895us 1 1 100.00
chip_sw_rstmgr_smoketest 177.010s 3674.218us 1 1 100.00
chip_sw_sram_ctrl_smoketest 193.060s 4266.674us 1 1 100.00
chip_sw_uart_smoketest 198.120s 3920.520us 1 1 100.00
chip_sw_otp_smoketest 1 1 100.00
chip_sw_otp_ctrl_smoketest 160.950s 3331.587us 1 1 100.00
chip_sw_rom_functests 0 1 0.00
rom_keymgr_functest 426.790s 5054.955us 0 1 0.00
chip_sw_boot 1 1 100.00
chip_sw_uart_tx_rx_bootstrap 10445.630s 61446.608us 1 1 100.00
chip_sw_secure_boot 1 1 100.00
rom_e2e_smoke 3510.230s 16335.903us 1 1 100.00
chip_sw_rom_raw_unlock 1 1 100.00
rom_raw_unlock 248.450s 7992.227us 1 1 100.00
chip_sw_power_idle_load 0 1 0.00
chip_sw_power_idle_load 1237.610s 16329.372us 0 1 0.00
chip_sw_power_sleep_load 0 1 0.00
chip_sw_power_sleep_load 681.220s 14961.662us 0 1 0.00
chip_sw_exit_test_unlocked_bootstrap 1 1 100.00
chip_sw_exit_test_unlocked_bootstrap 8316.700s 54911.954us 1 1 100.00
chip_sw_inject_scramble_seed 1 1 100.00
chip_sw_inject_scramble_seed 9399.260s 59791.258us 1 1 100.00
tl_d_oob_addr_access 0 1 0.00
chip_tl_errors 76.570s 2711.720us 0 1 0.00
tl_d_illegal_access 0 1 0.00
chip_tl_errors 76.570s 2711.720us 0 1 0.00
tl_d_outstanding_access 4 4 100.00
chip_csr_aliasing 5680.560s 38413.604us 1 1 100.00
chip_same_csr_outstanding 1637.020s 14757.585us 1 1 100.00
chip_csr_hw_reset 175.400s 4703.361us 1 1 100.00
chip_csr_rw 500.430s 6963.483us 1 1 100.00
tl_d_partial_access 4 4 100.00
chip_csr_aliasing 5680.560s 38413.604us 1 1 100.00
chip_same_csr_outstanding 1637.020s 14757.585us 1 1 100.00
chip_csr_hw_reset 175.400s 4703.361us 1 1 100.00
chip_csr_rw 500.430s 6963.483us 1 1 100.00
xbar_base_random_sequence 1 1 100.00
xbar_random 60.990s 2150.358us 1 1 100.00
xbar_random_delay 6 6 100.00
xbar_smoke_zero_delays 4.930s 48.503us 1 1 100.00
xbar_smoke_large_delays 48.830s 6819.846us 1 1 100.00
xbar_smoke_slow_rsp 53.620s 3782.165us 1 1 100.00
xbar_random_zero_delays 17.930s 224.687us 1 1 100.00
xbar_random_large_delays 129.950s 19426.186us 1 1 100.00
xbar_random_slow_rsp 172.590s 16811.411us 1 1 100.00
xbar_unmapped_address 2 2 100.00
xbar_unmapped_addr 50.770s 1309.479us 1 1 100.00
xbar_error_and_unmapped_addr 7.670s 71.326us 1 1 100.00
xbar_error_cases 2 2 100.00
xbar_error_random 28.630s 480.274us 1 1 100.00
xbar_error_and_unmapped_addr 7.670s 71.326us 1 1 100.00
xbar_all_access_same_device 2 2 100.00
xbar_access_same_device 52.320s 1848.761us 1 1 100.00
xbar_access_same_device_slow_rsp 402.140s 42490.515us 1 1 100.00
xbar_all_hosts_use_same_source_id 1 1 100.00
xbar_same_source 44.770s 1343.674us 1 1 100.00
xbar_stress_all 2 2 100.00
xbar_stress_all 216.430s 3164.873us 1 1 100.00
xbar_stress_all_with_error 162.420s 3011.962us 1 1 100.00
xbar_stress_with_reset 2 2 100.00
xbar_stress_all_with_rand_reset 25.040s 66.689us 1 1 100.00
xbar_stress_all_with_reset_error 132.590s 969.051us 1 1 100.00
rom_e2e_smoke 1 1 100.00
rom_e2e_smoke 3510.230s 16335.903us 1 1 100.00
rom_e2e_shutdown_output 1 1 100.00
rom_e2e_shutdown_output 2949.530s 31876.281us 1 1 100.00
rom_e2e_shutdown_exception_c 1 1 100.00
rom_e2e_shutdown_exception_c 3483.750s 16272.365us 1 1 100.00
rom_e2e_boot_policy_valid 15 15 100.00
rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 2728.080s 12159.977us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_dev 3520.920s 15297.671us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_prod 3489.690s 16168.642us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_prod_end 3578.130s 15227.488us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_rma 3548.930s 15926.806us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 2731.060s 12234.470us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_bad_dev 3509.060s 15751.741us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_bad_prod 3635.330s 16693.552us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_bad_prod_end 3567.490s 16284.776us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_bad_rma 3439.590s 16972.878us 1 1 100.00
rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 4848.040s 20990.433us 1 1 100.00
rom_e2e_boot_policy_valid_a_bad_b_good_dev 6277.940s 24812.971us 1 1 100.00
rom_e2e_boot_policy_valid_a_bad_b_good_prod 6256.680s 25668.368us 1 1 100.00
rom_e2e_boot_policy_valid_a_bad_b_good_prod_end 6414.150s 24424.788us 1 1 100.00
rom_e2e_boot_policy_valid_a_bad_b_good_rma 5960.930s 25049.358us 1 1 100.00
rom_e2e_sigverify_always 15 15 100.00
rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 4842.500s 17993.941us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_bad_dev 6044.970s 26019.613us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_bad_prod 5904.510s 23621.150us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_bad_prod_end 5847.270s 23396.624us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_bad_rma 5746.870s 22605.638us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 2637.100s 13856.923us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_nothing_dev 3086.340s 14664.995us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_nothing_prod 3185.170s 15182.746us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_nothing_prod_end 3233.470s 15689.397us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_nothing_rma 2986.190s 14391.621us 1 1 100.00
rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 2529.040s 13765.786us 1 1 100.00
rom_e2e_sigverify_always_a_nothing_b_bad_dev 3377.330s 14481.844us 1 1 100.00
rom_e2e_sigverify_always_a_nothing_b_bad_prod 3329.750s 15364.751us 1 1 100.00
rom_e2e_sigverify_always_a_nothing_b_bad_prod_end 3339.040s 16615.731us 1 1 100.00
rom_e2e_sigverify_always_a_nothing_b_bad_rma 3269.890s 17536.817us 1 1 100.00
rom_e2e_asm_init 5 5 100.00
rom_e2e_asm_init_test_unlocked0 2627.640s 12267.407us 1 1 100.00
rom_e2e_asm_init_dev 3401.460s 15305.478us 1 1 100.00
rom_e2e_asm_init_prod 3485.370s 17951.380us 1 1 100.00
rom_e2e_asm_init_prod_end 3594.320s 18165.683us 1 1 100.00
rom_e2e_asm_init_rma 3447.730s 16219.028us 1 1 100.00
rom_e2e_keymgr_init 3 3 100.00
rom_e2e_keymgr_init_rom_ext_meas 6606.520s 30741.873us 1 1 100.00
rom_e2e_keymgr_init_rom_ext_no_meas 6699.210s 30477.194us 1 1 100.00
rom_e2e_keymgr_init_rom_ext_invalid_meas 6744.640s 31075.173us 1 1 100.00
rom_e2e_static_critical 1 1 100.00
rom_e2e_static_critical 3509.310s 16162.754us 1 1 100.00
chip_sw_adc_ctrl_debug_cable_irq 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 3600.166s 0.000us 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 3600.166s 0.000us 0 1 0.00
chip_sw_aes_enc 2 2 100.00
chip_sw_aes_enc 206.340s 3432.248us 1 1 100.00
chip_sw_aes_enc_jitter_en 183.730s 3190.203us 1 1 100.00
chip_sw_aes_entropy 1 1 100.00
chip_sw_aes_entropy 227.950s 3320.639us 1 1 100.00
chip_sw_aes_idle 1 1 100.00
chip_sw_aes_idle 196.380s 3633.282us 1 1 100.00
chip_sw_aes_sideload 1 1 100.00
chip_sw_keymgr_sideload_aes 1987.920s 13715.939us 1 1 100.00
chip_sw_alert_handler_alerts 0 1 0.00
chip_sw_alert_test 213.580s 3797.102us 0 1 0.00
chip_sw_alert_handler_escalations 1 1 100.00
chip_sw_alert_handler_escalation 417.250s 5966.515us 1 1 100.00
chip_sw_all_escalation_resets 1 1 100.00
chip_sw_all_escalation_resets 485.050s 7099.602us 1 1 100.00
chip_sw_alert_handler_irqs 3 3 100.00
chip_plic_all_irqs_0 520.650s 4850.965us 1 1 100.00
chip_plic_all_irqs_10 319.870s 3908.380us 1 1 100.00
chip_plic_all_irqs_20 382.710s 4210.639us 1 1 100.00
chip_sw_alert_handler_entropy 1 1 100.00
chip_sw_alert_handler_entropy 212.450s 3477.967us 1 1 100.00
chip_sw_alert_handler_crashdump 1 1 100.00
chip_sw_rstmgr_alert_info 1483.060s 15268.843us 1 1 100.00
chip_sw_alert_handler_ping_timeout 1 1 100.00
chip_sw_alert_handler_ping_timeout 408.820s 5574.899us 1 1 100.00
chip_sw_alert_handler_lpg_sleep_mode_alerts 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_alerts 219.950s 3662.845us 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_pings 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_pings 14400.146s 0.000us 0 1 0.00
chip_sw_alert_handler_lpg_clock_off 1 1 100.00
chip_sw_alert_handler_lpg_clkoff 1658.500s 10311.170us 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 973.350s 7914.824us 1 1 100.00
chip_sw_alert_handler_ping_ok 1 1 100.00
chip_sw_alert_handler_ping_ok 835.780s 7812.063us 1 1 100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep 1 1 100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep 9644.720s 256744.660us 1 1 100.00
chip_sw_aon_timer_wakeup_irq 1 1 100.00
chip_sw_aon_timer_irq 332.130s 4751.275us 1 1 100.00
chip_sw_aon_timer_sleep_wakeup 1 1 100.00
chip_sw_pwrmgr_smoketest 470.830s 7806.374us 1 1 100.00
chip_sw_aon_timer_wdog_bark_irq 1 1 100.00
chip_sw_aon_timer_irq 332.130s 4751.275us 1 1 100.00
chip_sw_aon_timer_wdog_bite_reset 0 1 0.00
chip_sw_aon_timer_wdog_bite_reset 571.390s 9337.516us 0 1 0.00
chip_sw_aon_timer_sleep_wdog_bite_reset 0 1 0.00
chip_sw_aon_timer_wdog_bite_reset 571.390s 9337.516us 0 1 0.00
chip_sw_aon_timer_sleep_wdog_sleep_pause 1 1 100.00
chip_sw_aon_timer_sleep_wdog_sleep_pause 471.530s 9897.220us 1 1 100.00
chip_sw_aon_timer_wdog_lc_escalate 1 1 100.00
chip_sw_aon_timer_wdog_lc_escalate 512.570s 5623.957us 1 1 100.00
chip_sw_clkmgr_idle_trans 4 4 100.00
chip_sw_otbn_randomness 720.270s 7216.497us 1 1 100.00
chip_sw_aes_idle 196.380s 3633.282us 1 1 100.00
chip_sw_hmac_enc_idle 216.830s 4212.702us 1 1 100.00
chip_sw_kmac_idle 166.990s 3079.713us 1 1 100.00
chip_sw_clkmgr_off_trans 4 4 100.00
chip_sw_clkmgr_off_aes_trans 295.170s 4539.563us 1 1 100.00
chip_sw_clkmgr_off_hmac_trans 273.940s 5407.612us 1 1 100.00
chip_sw_clkmgr_off_kmac_trans 350.830s 6490.563us 1 1 100.00
chip_sw_clkmgr_off_otbn_trans 407.370s 6785.970us 1 1 100.00
chip_sw_clkmgr_off_peri 1 1 100.00
chip_sw_clkmgr_off_peri 882.250s 10962.596us 1 1 100.00
chip_sw_clkmgr_div 7 7 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 426.330s 4289.506us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 458.980s 4660.442us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 493.010s 5215.739us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 426.610s 5429.911us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_rma 441.470s 4977.105us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_rma 424.640s 5084.218us 1 1 100.00
chip_sw_ast_clk_outputs 704.720s 8136.352us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 412.710s 7891.594us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw 2 2 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 493.010s 5215.739us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 426.610s 5429.911us 1 1 100.00
chip_sw_clkmgr_jitter 10 10 100.00
chip_sw_flash_ctrl_ops_jitter_en 386.160s 4555.695us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 649.620s 5753.124us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 4395.020s 18971.013us 1 1 100.00
chip_sw_aes_enc_jitter_en 183.730s 3190.203us 1 1 100.00
chip_sw_edn_entropy_reqs_jitter 823.600s 7278.690us 1 1 100.00
chip_sw_hmac_enc_jitter_en 182.840s 3522.075us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 1354.290s 10008.567us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 230.950s 4449.610us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 529.180s 6794.124us 1 1 100.00
chip_sw_clkmgr_jitter 233.090s 3784.203us 1 1 100.00
chip_sw_clkmgr_extended_range 11 11 100.00
chip_sw_clkmgr_jitter_reduced_freq 171.880s 3212.503us 1 1 100.00
chip_sw_flash_ctrl_ops_jitter_en_reduced_freq 457.990s 5973.776us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en_reduced_freq 663.920s 7577.743us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq 4438.110s 25447.253us 1 1 100.00
chip_sw_aes_enc_jitter_en_reduced_freq 189.580s 4177.261us 1 1 100.00
chip_sw_hmac_enc_jitter_en_reduced_freq 224.550s 3941.432us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en_reduced_freq 1086.770s 10987.397us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en_reduced_freq 238.730s 3656.273us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq 520.510s 6174.136us 1 1 100.00
chip_sw_flash_init_reduced_freq 1468.210s 30871.080us 1 1 100.00
chip_sw_csrng_edn_concurrency_reduced_freq 14159.410s 127301.206us 1 1 100.00
chip_sw_clkmgr_deep_sleep_frequency 1 1 100.00
chip_sw_ast_clk_outputs 704.720s 8136.352us 1 1 100.00
chip_sw_clkmgr_sleep_frequency 1 1 100.00
chip_sw_clkmgr_sleep_frequency 482.060s 5721.333us 1 1 100.00
chip_sw_clkmgr_reset_frequency 1 1 100.00
chip_sw_clkmgr_reset_frequency 277.800s 3247.167us 1 1 100.00
chip_sw_clkmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 485.050s 7099.602us 1 1 100.00
chip_sw_clkmgr_alert_handler_clock_enables 1 1 100.00
chip_sw_alert_handler_lpg_clkoff 1658.500s 10311.170us 1 1 100.00
chip_sw_csrng_edn_cmd 1 1 100.00
chip_sw_entropy_src_csrng 1064.560s 6577.123us 1 1 100.00
chip_sw_csrng_fuse_en_sw_app_read 1 1 100.00
chip_sw_csrng_fuse_en_sw_app_read_test 334.120s 4622.012us 1 1 100.00
chip_sw_csrng_lc_hw_debug_en 1 1 100.00
chip_sw_csrng_lc_hw_debug_en_test 679.010s 10989.426us 1 1 100.00
chip_sw_csrng_known_answer_tests 1 1 100.00
chip_sw_csrng_kat_test 251.670s 3024.930us 1 1 100.00
chip_sw_edn_entropy_reqs 3 3 100.00
chip_sw_csrng_edn_concurrency 4011.280s 20190.368us 1 1 100.00
chip_sw_entropy_src_ast_rng_req 200.620s 4264.678us 1 1 100.00
chip_sw_edn_entropy_reqs 789.830s 6158.451us 1 1 100.00
chip_sw_entropy_src_ast_rng_req 1 1 100.00
chip_sw_entropy_src_ast_rng_req 200.620s 4264.678us 1 1 100.00
chip_sw_entropy_src_csrng 1 1 100.00
chip_sw_entropy_src_csrng 1064.560s 6577.123us 1 1 100.00
chip_sw_entropy_src_known_answer_tests 1 1 100.00
chip_sw_entropy_src_kat_test 187.360s 3490.307us 1 1 100.00
chip_sw_flash_init 1 1 100.00
chip_sw_flash_init 1250.470s 23909.746us 1 1 100.00
chip_sw_flash_host_access 2 2 100.00
chip_sw_flash_ctrl_access 614.800s 6142.868us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 649.620s 5753.124us 1 1 100.00
chip_sw_flash_ctrl_ops 2 2 100.00
chip_sw_flash_ctrl_ops 452.820s 4636.791us 1 1 100.00
chip_sw_flash_ctrl_ops_jitter_en 386.160s 4555.695us 1 1 100.00
chip_sw_flash_rma_unlocked 1 1 100.00
chip_sw_flash_rma_unlocked 4559.380s 45709.662us 1 1 100.00
chip_sw_flash_scramble 1 1 100.00
chip_sw_flash_init 1250.470s 23909.746us 1 1 100.00
chip_sw_flash_idle_low_power 1 1 100.00
chip_sw_flash_ctrl_idle_low_power 277.680s 3869.716us 1 1 100.00
chip_sw_flash_keymgr_seeds 1 1 100.00
chip_sw_keymgr_key_derivation 810.860s 8416.670us 1 1 100.00
chip_sw_flash_lc_creator_seed_sw_rw_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 182.980s 3407.135us 0 1 0.00
chip_sw_flash_creator_seed_wipe_on_rma 1 1 100.00
chip_sw_flash_rma_unlocked 4559.380s 45709.662us 1 1 100.00
chip_sw_flash_lc_owner_seed_sw_rw_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 182.980s 3407.135us 0 1 0.00
chip_sw_flash_lc_iso_part_sw_rd_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 182.980s 3407.135us 0 1 0.00
chip_sw_flash_lc_iso_part_sw_wr_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 182.980s 3407.135us 0 1 0.00
chip_sw_flash_lc_seed_hw_rd_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 182.980s 3407.135us 0 1 0.00
chip_sw_flash_lc_escalate_en 1 1 100.00
chip_sw_all_escalation_resets 485.050s 7099.602us 1 1 100.00
chip_sw_flash_prim_tl_access 1 1 100.00
chip_prim_tl_access 379.240s 10244.582us 1 1 100.00
chip_sw_flash_ctrl_clock_freqs 1 1 100.00
chip_sw_flash_ctrl_clock_freqs 654.100s 5960.181us 1 1 100.00
chip_sw_flash_ctrl_escalation_reset 1 1 100.00
chip_sw_flash_crash_alert 536.200s 7220.621us 1 1 100.00
chip_sw_flash_ctrl_write_clear 1 1 100.00
chip_sw_flash_crash_alert 536.200s 7220.621us 1 1 100.00
chip_sw_hmac_enc 2 2 100.00
chip_sw_hmac_enc 161.490s 3929.951us 1 1 100.00
chip_sw_hmac_enc_jitter_en 182.840s 3522.075us 1 1 100.00
chip_sw_hmac_idle 1 1 100.00
chip_sw_hmac_enc_idle 216.830s 4212.702us 1 1 100.00
chip_sw_hmac_all_configurations 1 1 100.00
chip_sw_hmac_oneshot 923.640s 6737.826us 1 1 100.00
chip_sw_hmac_multistream_mode 0 1 0.00
chip_sw_hmac_multistream 1885.490s 12026.803us 0 1 0.00
chip_sw_i2c_host_tx_rx 3 3 100.00
chip_sw_i2c_host_tx_rx 312.350s 3793.304us 1 1 100.00
chip_sw_i2c_host_tx_rx_idx1 573.740s 6918.640us 1 1 100.00
chip_sw_i2c_host_tx_rx_idx2 503.830s 6857.718us 1 1 100.00
chip_sw_i2c_device_tx_rx 1 1 100.00
chip_sw_i2c_device_tx_rx 378.070s 5414.023us 1 1 100.00
chip_sw_keymgr_key_derivation 2 2 100.00
chip_sw_keymgr_key_derivation 810.860s 8416.670us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 1354.290s 10008.567us 1 1 100.00
chip_sw_keymgr_sideload_kmac 1 1 100.00
chip_sw_keymgr_sideload_kmac 1537.700s 11481.547us 1 1 100.00
chip_sw_keymgr_sideload_aes 1 1 100.00
chip_sw_keymgr_sideload_aes 1987.920s 13715.939us 1 1 100.00
chip_sw_keymgr_sideload_otbn 0 1 0.00
chip_sw_keymgr_sideload_otbn 5866.010s 20026.667us 0 1 0.00
chip_sw_kmac_enc 3 3 100.00
chip_sw_kmac_mode_cshake 208.250s 3931.177us 1 1 100.00
chip_sw_kmac_mode_kmac 267.920s 3800.656us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 230.950s 4449.610us 1 1 100.00
chip_sw_kmac_app_keymgr 1 1 100.00
chip_sw_keymgr_key_derivation 810.860s 8416.670us 1 1 100.00
chip_sw_kmac_app_lc 1 1 100.00
chip_sw_lc_ctrl_transition 999.860s 14317.314us 1 1 100.00
chip_sw_kmac_app_rom 1 1 100.00
chip_sw_kmac_app_rom 183.210s 3378.593us 1 1 100.00
chip_sw_kmac_entropy 1 1 100.00
chip_sw_kmac_entropy 749.490s 6996.593us 1 1 100.00
chip_sw_kmac_idle 1 1 100.00
chip_sw_kmac_idle 166.990s 3079.713us 1 1 100.00
chip_sw_lc_ctrl_alert_handler_escalation 1 1 100.00
chip_sw_alert_handler_escalation 417.250s 5966.515us 1 1 100.00
chip_sw_lc_ctrl_jtag_access 3 3 100.00
chip_tap_straps_dev 109.000s 2974.299us 1 1 100.00
chip_tap_straps_rma 527.440s 8431.211us 1 1 100.00
chip_tap_straps_prod 142.630s 3497.886us 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 200.920s 3736.061us 1 1 100.00
chip_sw_lc_ctrl_init 1 1 100.00
chip_sw_lc_ctrl_transition 999.860s 14317.314us 1 1 100.00
chip_sw_lc_ctrl_transitions 1 1 100.00
chip_sw_lc_ctrl_transition 999.860s 14317.314us 1 1 100.00
chip_sw_lc_ctrl_kmac_req 1 1 100.00
chip_sw_lc_ctrl_transition 999.860s 14317.314us 1 1 100.00
chip_sw_lc_ctrl_key_div 1 1 100.00
chip_sw_keymgr_key_derivation_prod 1500.550s 10583.557us 1 1 100.00
chip_sw_lc_ctrl_broadcast 19 22 86.36
chip_sw_flash_ctrl_lc_rw_en 182.980s 3407.135us 0 1 0.00
chip_sw_flash_rma_unlocked 4559.380s 45709.662us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_test_unlocked0 249.540s 3126.526us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_dev 754.440s 8214.337us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_prod 687.820s 8339.289us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_rma 604.940s 7402.892us 0 1 0.00
chip_sw_lc_ctrl_transition 999.860s 14317.314us 1 1 100.00
chip_sw_keymgr_key_derivation 810.860s 8416.670us 1 1 100.00
chip_sw_rom_ctrl_integrity_check 418.670s 11258.811us 1 1 100.00
chip_sw_sram_ctrl_execution_main 624.640s 10815.748us 1 1 100.00
chip_prim_tl_access 379.240s 10244.582us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 412.710s 7891.594us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 426.330s 4289.506us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 458.980s 4660.442us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 493.010s 5215.739us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 426.610s 5429.911us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_rma 441.470s 4977.105us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_rma 424.640s 5084.218us 1 1 100.00
chip_tap_straps_dev 109.000s 2974.299us 1 1 100.00
chip_tap_straps_rma 527.440s 8431.211us 1 1 100.00
chip_tap_straps_prod 142.630s 3497.886us 1 1 100.00
chip_rv_dm_lc_disabled 233.520s 7161.744us 0 1 0.00
chip_lc_scrap 4 4 100.00
chip_sw_lc_ctrl_rma_to_scrap 194.000s 4075.311us 1 1 100.00
chip_sw_lc_ctrl_raw_to_scrap 135.730s 3862.690us 1 1 100.00
chip_sw_lc_ctrl_test_locked0_to_scrap 113.750s 4461.592us 1 1 100.00
chip_sw_lc_ctrl_rand_to_scrap 181.460s 3693.999us 1 1 100.00
chip_lc_test_locked 0 2 0.00
chip_sw_lc_walkthrough_testunlocks 2355.610s 57585.636us 0 1 0.00
chip_rv_dm_lc_disabled 233.520s 7161.744us 0 1 0.00
chip_sw_lc_walkthrough 1 5 20.00
chip_sw_lc_walkthrough_dev 771.900s 10323.622us 0 1 0.00
chip_sw_lc_walkthrough_prod 731.150s 13776.039us 0 1 0.00
chip_sw_lc_walkthrough_prodend 874.990s 10494.432us 1 1 100.00
chip_sw_lc_walkthrough_rma 519.370s 8071.119us 0 1 0.00
chip_sw_lc_walkthrough_testunlocks 2355.610s 57585.636us 0 1 0.00
chip_sw_lc_ctrl_volatile_raw_unlock 3 3 100.00
chip_sw_lc_ctrl_volatile_raw_unlock 84.320s 2586.740us 1 1 100.00
chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz 90.600s 2640.877us 1 1 100.00
rom_volatile_raw_unlock 75.300s 3243.575us 1 1 100.00
chip_sw_otbn_op 2 2 100.00
chip_sw_otbn_ecdsa_op_irq 4139.680s 18220.743us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 4395.020s 18971.013us 1 1 100.00
chip_sw_otbn_rnd_entropy 1 1 100.00
chip_sw_otbn_randomness 720.270s 7216.497us 1 1 100.00
chip_sw_otbn_urnd_entropy 1 1 100.00
chip_sw_otbn_randomness 720.270s 7216.497us 1 1 100.00
chip_sw_otbn_idle 1 1 100.00
chip_sw_otbn_randomness 720.270s 7216.497us 1 1 100.00
chip_sw_otbn_mem_scramble 1 1 100.00
chip_sw_otbn_mem_scramble 334.410s 3831.236us 1 1 100.00
chip_otp_ctrl_init 1 1 100.00
chip_sw_lc_ctrl_transition 999.860s 14317.314us 1 1 100.00
chip_sw_otp_ctrl_keys 5 5 100.00
chip_sw_flash_init 1250.470s 23909.746us 1 1 100.00
chip_sw_otbn_mem_scramble 334.410s 3831.236us 1 1 100.00
chip_sw_keymgr_key_derivation 810.860s 8416.670us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access 485.790s 5647.707us 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 225.010s 4072.108us 1 1 100.00
chip_sw_otp_ctrl_entropy 5 5 100.00
chip_sw_flash_init 1250.470s 23909.746us 1 1 100.00
chip_sw_otbn_mem_scramble 334.410s 3831.236us 1 1 100.00
chip_sw_keymgr_key_derivation 810.860s 8416.670us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access 485.790s 5647.707us 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 225.010s 4072.108us 1 1 100.00
chip_sw_otp_ctrl_program 1 1 100.00
chip_sw_lc_ctrl_transition 999.860s 14317.314us 1 1 100.00
chip_sw_otp_ctrl_program_error 1 1 100.00
chip_sw_lc_ctrl_program_error 398.930s 5733.317us 1 1 100.00
chip_sw_otp_ctrl_hw_cfg0 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 200.920s 3736.061us 1 1 100.00
chip_sw_otp_ctrl_lc_signals 5 6 83.33
chip_sw_otp_ctrl_lc_signals_test_unlocked0 249.540s 3126.526us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_dev 754.440s 8214.337us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_prod 687.820s 8339.289us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_rma 604.940s 7402.892us 0 1 0.00
chip_sw_lc_ctrl_transition 999.860s 14317.314us 1 1 100.00
chip_prim_tl_access 379.240s 10244.582us 1 1 100.00
chip_sw_otp_prim_tl_access 1 1 100.00
chip_prim_tl_access 379.240s 10244.582us 1 1 100.00
chip_sw_otp_ctrl_dai_lock 1 1 100.00
chip_sw_otp_ctrl_dai_lock 986.610s 8381.268us 1 1 100.00
chip_sw_pwrmgr_external_full_reset 0 1 0.00
chip_sw_pwrmgr_full_aon_reset 233.780s 6630.987us 0 1 0.00
chip_sw_pwrmgr_random_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_wake_ups 1503.360s 28573.408us 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups 306.800s 8462.973us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_por_reset 0 1 0.00
chip_sw_pwrmgr_deep_sleep_por_reset 396.670s 8900.128us 0 1 0.00
chip_sw_pwrmgr_normal_sleep_por_reset 1 1 100.00
chip_sw_pwrmgr_normal_sleep_por_reset 559.620s 8486.222us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups 902.000s 26736.852us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 0 2 0.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 310.000s 6305.171us 0 1 0.00
chip_sw_aon_timer_wdog_bite_reset 571.390s 9337.516us 0 1 0.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 823.930s 15202.852us 1 1 100.00
chip_sw_pwrmgr_wdog_reset 1 1 100.00
chip_sw_pwrmgr_wdog_reset 448.460s 5391.752us 1 1 100.00
chip_sw_pwrmgr_power_glitch_reset 0 1 0.00
chip_sw_pwrmgr_full_aon_reset 233.780s 6630.987us 0 1 0.00
chip_sw_pwrmgr_main_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_main_power_glitch_reset 376.090s 6737.129us 1 1 100.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset 0 1 0.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset 491.520s 9424.046us 0 1 0.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset 377.810s 7625.371us 1 1 100.00
chip_sw_pwrmgr_sleep_power_glitch_reset 0 1 0.00
chip_sw_pwrmgr_sleep_power_glitch_reset 165.700s 3044.350us 0 1 0.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 0 1 0.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 633.020s 11951.450us 0 1 0.00
chip_sw_pwrmgr_sysrst_ctrl_reset 2 2 100.00
chip_sw_pwrmgr_sysrst_ctrl_reset 800.510s 10652.804us 1 1 100.00
chip_sw_pwrmgr_all_reset_reqs 1292.130s 15128.428us 1 1 100.00
chip_sw_pwrmgr_b2b_sleep_reset_req 1 1 100.00
chip_sw_pwrmgr_b2b_sleep_reset_req 2421.840s 40723.367us 1 1 100.00
chip_sw_pwrmgr_sleep_disabled 1 1 100.00
chip_sw_pwrmgr_sleep_disabled 178.180s 2994.413us 1 1 100.00
chip_sw_pwrmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 485.050s 7099.602us 1 1 100.00
chip_sw_rom_access 1 1 100.00
chip_sw_rom_ctrl_integrity_check 418.670s 11258.811us 1 1 100.00
chip_sw_rom_ctrl_integrity_check 1 1 100.00
chip_sw_rom_ctrl_integrity_check 418.670s 11258.811us 1 1 100.00
chip_sw_rstmgr_non_sys_reset_info 3 4 75.00
chip_sw_pwrmgr_all_reset_reqs 1292.130s 15128.428us 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 633.020s 11951.450us 0 1 0.00
chip_sw_pwrmgr_wdog_reset 448.460s 5391.752us 1 1 100.00
chip_sw_pwrmgr_smoketest 470.830s 7806.374us 1 1 100.00
chip_sw_rstmgr_sys_reset_info 1 1 100.00
chip_rv_dm_ndm_reset_req 307.680s 4267.439us 1 1 100.00
chip_sw_rstmgr_cpu_info 1 1 100.00
chip_sw_rstmgr_cpu_info 627.030s 9156.982us 1 1 100.00
chip_sw_rstmgr_sw_req_reset 1 1 100.00
chip_sw_rstmgr_sw_req 326.330s 6165.278us 1 1 100.00
chip_sw_rstmgr_alert_info 1 1 100.00
chip_sw_rstmgr_alert_info 1483.060s 15268.843us 1 1 100.00
chip_sw_rstmgr_sw_rst 1 1 100.00
chip_sw_rstmgr_sw_rst 162.510s 3519.904us 1 1 100.00
chip_sw_rstmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 485.050s 7099.602us 1 1 100.00
chip_sw_rstmgr_alert_handler_reset_enables 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 973.350s 7914.824us 1 1 100.00
chip_sw_nmi_irq 1 1 100.00
chip_sw_rv_core_ibex_nmi_irq 517.150s 5486.249us 1 1 100.00
chip_sw_rv_core_ibex_rnd 1 1 100.00
chip_sw_rv_core_ibex_rnd 559.200s 5237.356us 1 1 100.00
chip_sw_rv_core_ibex_address_translation 1 1 100.00
chip_sw_rv_core_ibex_address_translation 256.600s 4485.743us 1 1 100.00
chip_sw_rv_core_ibex_icache_scrambled_access 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 225.010s 4072.108us 1 1 100.00
chip_sw_rv_core_ibex_fault_dump 1 1 100.00
chip_sw_rstmgr_cpu_info 627.030s 9156.982us 1 1 100.00
chip_sw_rv_core_ibex_double_fault 1 1 100.00
chip_sw_rstmgr_cpu_info 627.030s 9156.982us 1 1 100.00
chip_sw_rv_core_ibex_mcounteren_writable 1 1 100.00
chip_sw_rv_core_ibex_mcounteren_writable 188.140s 3114.865us 1 1 100.00
chip_jtag_csr_rw 1 1 100.00
chip_jtag_csr_rw 1351.050s 17394.428us 1 1 100.00
chip_jtag_mem_access 1 1 100.00
chip_jtag_mem_access 1148.950s 17090.750us 1 1 100.00
chip_rv_dm_ndm_reset_req 1 1 100.00
chip_rv_dm_ndm_reset_req 307.680s 4267.439us 1 1 100.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 0 1 0.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 253.580s 3171.642us 0 1 0.00
chip_rv_dm_access_after_wakeup 0 1 0.00
chip_sw_rv_dm_access_after_wakeup 1549.480s 12944.841us 0 1 0.00
chip_sw_rv_dm_jtag_tap_sel 1 1 100.00
chip_tap_straps_rma 527.440s 8431.211us 1 1 100.00
chip_rv_dm_lc_disabled 0 1 0.00
chip_rv_dm_lc_disabled 233.520s 7161.744us 0 1 0.00
chip_sw_plic_all_irqs 3 3 100.00
chip_plic_all_irqs_0 520.650s 4850.965us 1 1 100.00
chip_plic_all_irqs_10 319.870s 3908.380us 1 1 100.00
chip_plic_all_irqs_20 382.710s 4210.639us 1 1 100.00
chip_sw_plic_sw_irq 1 1 100.00
chip_sw_plic_sw_irq 161.530s 2926.108us 1 1 100.00
chip_sw_timer 1 1 100.00
chip_sw_rv_timer_irq 240.560s 3463.549us 1 1 100.00
chip_sw_spi_device_flash_mode 1 1 100.00
rom_e2e_smoke 3510.230s 16335.903us 1 1 100.00
chip_sw_spi_device_pass_through 1 1 100.00
chip_sw_spi_device_pass_through 543.700s 7126.658us 1 1 100.00
chip_sw_spi_device_pass_through_collision 0 1 0.00
chip_sw_spi_device_pass_through_collision 252.990s 3444.789us 0 1 0.00
chip_sw_spi_device_tpm 1 1 100.00
chip_sw_spi_device_tpm 256.170s 3910.277us 1 1 100.00
chip_sw_spi_host_tx_rx 1 1 100.00
chip_sw_spi_host_tx_rx 222.990s 3345.108us 1 1 100.00
chip_sw_sram_scrambled_access 2 2 100.00
chip_sw_sram_ctrl_scrambled_access 485.790s 5647.707us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 529.180s 6794.124us 1 1 100.00
chip_sw_sleep_sram_ret_contents 2 2 100.00
chip_sw_sleep_sram_ret_contents_no_scramble 578.390s 10610.202us 1 1 100.00
chip_sw_sleep_sram_ret_contents_scramble 447.540s 11279.598us 1 1 100.00
chip_sw_sram_execution 1 1 100.00
chip_sw_sram_ctrl_execution_main 624.640s 10815.748us 1 1 100.00
chip_sw_sram_lc_escalation 2 2 100.00
chip_sw_all_escalation_resets 485.050s 7099.602us 1 1 100.00
chip_sw_data_integrity_escalation 611.290s 7229.522us 1 1 100.00
chip_sw_sysrst_ctrl_reset 1 2 50.00
chip_sw_pwrmgr_sysrst_ctrl_reset 800.510s 10652.804us 1 1 100.00
chip_sw_sysrst_ctrl_reset 1157.250s 24599.400us 0 1 0.00
chip_sw_sysrst_ctrl_inputs 1 1 100.00
chip_sw_sysrst_ctrl_inputs 226.330s 3357.080us 1 1 100.00
chip_sw_sysrst_ctrl_outputs 1 1 100.00
chip_sw_sysrst_ctrl_outputs 257.880s 4185.145us 1 1 100.00
chip_sw_sysrst_ctrl_in_irq 1 1 100.00
chip_sw_sysrst_ctrl_in_irq 423.220s 5605.324us 1 1 100.00
chip_sw_sysrst_ctrl_sleep_wakeup 0 1 0.00
chip_sw_sysrst_ctrl_reset 1157.250s 24599.400us 0 1 0.00
chip_sw_sysrst_ctrl_sleep_reset 0 1 0.00
chip_sw_sysrst_ctrl_reset 1157.250s 24599.400us 0 1 0.00
chip_sw_sysrst_ctrl_ec_rst_l 1 1 100.00
chip_sw_sysrst_ctrl_ec_rst_l 2568.900s 20607.829us 1 1 100.00
chip_sw_sysrst_ctrl_flash_wp_l 1 1 100.00
chip_sw_sysrst_ctrl_ec_rst_l 2568.900s 20607.829us 1 1 100.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup 1 2 50.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup 423.400s 7444.793us 1 1 100.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 3600.166s 0.000us 0 1 0.00
chip_sw_usbdev_vbus 1 1 100.00
chip_sw_usbdev_vbus 202.210s 3578.997us 1 1 100.00
chip_sw_usbdev_pullup 1 1 100.00
chip_sw_usbdev_pullup 159.260s 3092.550us 1 1 100.00
chip_sw_usbdev_aon_pullup 1 1 100.00
chip_sw_usbdev_aon_pullup 348.400s 3620.497us 1 1 100.00
chip_sw_usbdev_setup_rx 1 1 100.00
chip_sw_usbdev_setuprx 409.250s 4895.887us 1 1 100.00
chip_sw_usbdev_config_host 1 1 100.00
chip_sw_usbdev_config_host 1065.790s 9061.636us 1 1 100.00
chip_sw_usbdev_pincfg 1 1 100.00
chip_sw_usbdev_pincfg 6431.420s 32437.150us 1 1 100.00
chip_sw_usbdev_tx_rx 1 1 100.00
chip_sw_usbdev_dpi 2203.680s 12628.645us 1 1 100.00
chip_sw_usbdev_toggle_restore 1 1 100.00
chip_sw_usbdev_toggle_restore 258.100s 3332.577us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_aes_masking_off 1 1 100.00
chip_sw_aes_masking_off 200.030s 2880.751us 1 1 100.00
chip_sw_rv_core_ibex_lockstep_glitch 0 1 0.00
chip_sw_rv_core_ibex_lockstep_glitch 149.830s 3499.593us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_coremark 1 1 100.00
chip_sw_coremark 12009.190s 68811.053us 1 1 100.00
chip_sw_power_max_load 1 1 100.00
chip_sw_power_virus 1143.460s 6552.121us 1 1 100.00
rom_e2e_debug 0 3 0.00
rom_e2e_jtag_debug_test_unlocked0 250.000s 5313.405us 0 1 0.00
rom_e2e_jtag_debug_dev 232.810s 4404.446us 0 1 0.00
rom_e2e_jtag_debug_rma 669.170s 15758.346us 0 1 0.00
rom_e2e_jtag_inject 0 3 0.00
rom_e2e_jtag_inject_test_unlocked0 210.070s 5272.944us 0 1 0.00
rom_e2e_jtag_inject_dev 86.590s 1994.631us 0 1 0.00
rom_e2e_jtag_inject_rma 110.510s 3053.978us 0 1 0.00
rom_e2e_self_hash 0 1 0.00
rom_e2e_self_hash 121.815s 0.000us 0 1 0.00
chip_sw_clkmgr_jitter_cycle_measurements 0 1 0.00
chip_sw_clkmgr_jitter_frequency 342.540s 4633.398us 0 1 0.00
chip_sw_edn_boot_mode 1 1 100.00
chip_sw_edn_boot_mode 399.260s 3103.548us 1 1 100.00
chip_sw_edn_auto_mode 1 1 100.00
chip_sw_edn_auto_mode 774.970s 5334.554us 1 1 100.00
chip_sw_edn_sw_mode 1 1 100.00
chip_sw_edn_sw_mode 1637.940s 11848.848us 1 1 100.00
chip_sw_edn_kat 1 1 100.00
chip_sw_edn_kat 267.660s 2857.323us 1 1 100.00
chip_sw_flash_memory_protection 1 1 100.00
chip_sw_flash_ctrl_mem_protection 640.110s 5607.927us 1 1 100.00
chip_sw_otp_ctrl_vendor_test_csr_access 1 1 100.00
chip_sw_otp_ctrl_vendor_test_csr_access 200.020s 3578.985us 1 1 100.00
chip_sw_otp_ctrl_escalation 0 1 0.00
chip_sw_otp_ctrl_escalation 205.630s 4022.749us 0 1 0.00
chip_sw_sensor_ctrl_deep_sleep_wake_up 1 1 100.00
chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up 328.550s 6922.216us 1 1 100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active 1 1 100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active 329.310s 7028.519us 1 1 100.00
chip_sw_all_resets 1 1 100.00
chip_sw_pwrmgr_all_reset_reqs 1292.130s 15128.428us 1 1 100.00
chip_rv_dm_perform_debug 0 3 0.00
rom_e2e_jtag_debug_test_unlocked0 250.000s 5313.405us 0 1 0.00
rom_e2e_jtag_debug_dev 232.810s 4404.446us 0 1 0.00
rom_e2e_jtag_debug_rma 669.170s 15758.346us 0 1 0.00
chip_sw_rv_dm_access_after_hw_reset 1 1 100.00
chip_sw_rv_dm_access_after_escalation_reset 539.650s 6618.484us 1 1 100.00
chip_sw_plic_alerts 1 1 100.00
chip_sw_all_escalation_resets 485.050s 7099.602us 1 1 100.00
tick_configuration 1 1 100.00
chip_sw_rv_timer_systick_test 5980.780s 39128.270us 1 1 100.00
counter_wrap 1 1 100.00
chip_sw_rv_timer_systick_test 5980.780s 39128.270us 1 1 100.00
chip_sw_spi_device_output_when_disabled_or_sleeping 1 1 100.00
chip_sw_spi_device_pinmux_sleep_retention 206.080s 4309.594us 1 1 100.00
chip_sw_uart_watermarks 1 1 100.00
chip_sw_uart_tx_rx 403.420s 5040.904us 1 1 100.00
chip_sw_usbdev_stream 1 1 100.00
chip_sw_usbdev_stream 3580.690s 19069.134us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 7 11 63.64
chip_sival_flash_info_access 225.230s 3234.477us 1 1 100.00
chip_sw_rstmgr_rst_cnsty_escalation 21.680s 10.380us 0 1 0.00
chip_sw_otp_ctrl_rot_auth_config 6.120s 0.000us 0 1 0.00
chip_sw_otp_ctrl_ecc_error_vendor_test 229.000s 3643.469us 1 1 100.00
chip_sw_otp_ctrl_descrambling 263.730s 3374.644us 1 1 100.00
chip_sw_pwrmgr_lowpower_cancel 263.960s 4644.687us 1 1 100.00
chip_sw_pwrmgr_sleep_wake_5_bug 9.088s 0.000us 0 1 0.00
chip_sw_flash_ctrl_write_clear 245.080s 3837.631us 1 1 100.00
ate_bootstrap_flash_erase 766.180s 10010.160us 0 1 0.00
ate_bootstrap_one_frame 7374.480s 44203.201us 1 1 100.00
ate_bootstrap_disjoint 10291.050s 80008.166us 1 1 100.00

Error Messages

   Test seed line log context
Offending '(rstreqs[*] && (reset_cause == HwReq))' 6 test runs
chip_sw_pwrmgr_random_sleep_all_reset_reqs 70020911275034998379195947828810505614309785501292854213707138601135215329621 347
UVM_ERROR @ 11951.450000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 11951.450000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 82011354829360030346673274300268537122697569934970116864349808500092436858332 317
UVM_ERROR @ 6305.171000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 6305.171000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_deep_sleep_por_reset 9958491442556205367052812043143803654487826646979694402907828775362380335211 328
UVM_ERROR @ 8900.128000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 8900.128000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_random_sleep_power_glitch_reset 33780464655739272037906068136326068316275097494299747648517023012711171778429 333
UVM_ERROR @ 9424.046000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 9424.046000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_sysrst_ctrl_reset 34215380386136008932249134358014619182250687658238985064414348544601551080570 337
UVM_ERROR @ 24599.400000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 24599.400000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_aon_timer_wdog_bite_reset 29313872087474474110270685436940225648031362560801544337219943432809208500994 322
UVM_ERROR @ 9337.516500 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 9337.516500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Error-[NOA] Null object access 4 test runs
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 85117037061872566379423541861034414376240595890380515948625673551622320894112 330
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_test_unlocked0 61535612346453378832881247912877691993206914989425632049943750322506432367469 313
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_dev 16006703192325315928582191738742156571428486304608353794008736039168129674161 306
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_rma 45219115589643956987344140699622455779146712222101041444211190411774613838000 306
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected 3 test runs
chip_sw_lc_walkthrough_dev 103464654568301253761907667619954055016867984085745215272942167038947064308617 372
UVM_INFO @ 10323.621850 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_prod 48643570811220746273833359495112047453835746842168491194015756504200562370214 372
UVM_INFO @ 13776.039260 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_rma 90406169398535020191880483585826563348929530849159807701240623663341796357084 344
UVM_INFO @ 8071.119350 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes 2 test runs
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 74747480827618196420103302685580055996109369670699416232382414655035367713845 None
chip_sw_alert_handler_lpg_sleep_mode_pings 12301808122837042079196001542014715348625173548346501679772764829880288583665 None
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:322) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns 2 test runs
chip_sw_hmac_multistream 12595834239618957690810478095261171545864742652589188617992447153112055793715 371
UVM_INFO @ 12026.803091 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_keymgr_sideload_otbn 107458855799426260771850228950197696778466653857888121227986471217534787937845 341
UVM_INFO @ 20026.667164 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:615) scoreboard [scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted *, but saw *). 2 test runs
chip_tl_errors 101888900918902546905098083450065006204113322137361437658953848893716685538620 220
TL item was: req: (cip_tl_seq_item@32741) { a_addr: 'h10780 a_data: 'h2e742f32 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h21 a_opcode: 'h4 a_user: 'h1a91f d_param: 'h0 d_source: 'h21 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2711.720329 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_csr_mem_rw_with_rand_reset 111948258427329261229443949609445949653581508376740068967738171478651113725506 227
TL item was: req: (cip_tl_seq_item@31925) { a_addr: 'h104cc a_data: 'h143d21a1 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h6 a_opcode: 'h4 a_user: 'h195a0 d_param: 'h0 d_source: 'h6 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2427.553806 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$'] 2 test runs
chip_sw_pwrmgr_sleep_wake_5_bug 40939198135771500573813658648606939311285127455837780339167370384589244550254 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_self_hash 43254926813960233909947682966224661088036712532529366081602196173257790663432 None
Another command (pid=532036) is running. Waiting for it to complete on the server (server_pid=259727)...
Another command (pid=573998) is running. Waiting for it to complete on the server (server_pid=259727)...
Another command (pid=578022) is running. Waiting for it to complete on the server (server_pid=259727)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
UVM_FATAL @ * us: (sec_cm_pkg.sv:48) [sec_cm_pkg::find_sec_cm_if_proxy] no proxy with path *rstmgr.u_d0_spi_host*.leaf_rst_path 1 test run
chip_sw_rstmgr_rst_cnsty_escalation 10194341426236937689924696589323114112765456664581443237990820627804531542997 304
UVM_INFO @ 10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$isunknown(pin_wkup_req_o))' 1 test run
chip_sw_sleep_pin_wake 44128061488713201067874789222446127378000853719737711874678903032070571043978 321
UVM_ERROR @ 3575.269000 us: (pinmux.sv:662) [ASSERT FAILED] AonWkupReqKnownO_A
UVM_INFO @ 3575.269000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty 1 test run
chip_sw_spi_device_pass_through_collision 40104210815969516025105586416385792868072874947918062128625041097735293703235 330
UVM_INFO @ 3444.788572 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [flash_ctrl_lc_rw_en_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected 1 test run
chip_sw_flash_ctrl_lc_rw_en 109264166776971632794996769556158073788332851613020568844240487269869615884097 312
UVM_INFO @ 3407.135338 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to * 1 test run
chip_sw_otp_ctrl_lc_signals_rma 75841195387228753940543852790472134667718062549545444318675898329657619970657 345
UVM_INFO @ 7402.892178 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))' 1 test run
chip_sw_otp_ctrl_escalation 2401779130613661264381615372071207019776422440733397112580784694123057328491 319
UVM_ERROR @ 4022.748520 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 4022.748520 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[Otp]] file otp_img_test_unlocked0_manuf_empty.*.vmem could not be opened for r mode 1 test run
chip_sw_otp_ctrl_rot_auth_config 103482058011398240645389236224917821460569841967188502233883964389659232017463 285
UVM_INFO @ 0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_base_vseq.sv:864) virtual_sequencer [chip_sw_lc_walkthrough_testunlocks_vseq] max attempt reached to get lc status LcExtClockSwitched! 1 test run
chip_sw_lc_walkthrough_testunlocks 52412340973615104623987042034570162612033284870574975073146845942780144044830 474
UVM_INFO @ 57585.635920 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '((~rst_ni) === (~seed_en_q))' 1 test run
chip_sw_pwrmgr_full_aon_reset 35372879695113047225733631532138369173933831340515775811487826418184648510363 323
UVM_ERROR @ 6630.986704 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A
UVM_INFO @ 6630.986704 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$fell((pwrmgr_data_o.done == MuBi4True)))' 1 test run
chip_sw_pwrmgr_sleep_power_glitch_reset 17590894637661364520341232425217223938091184309680587254885903696338662103312 316
UVM_ERROR @ 3044.350311 us: (rom_ctrl.sv:590) [ASSERT FAILED] PwrmgrDataChk_A
UVM_INFO @ 3044.350311 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:351)] CHECK-fail: Expect alert *! 1 test run
chip_sw_alert_test 74446438962339670485100510374146722829855029152645099636899485829158648276481 310
UVM_INFO @ 3797.102036 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0) 1 test run
chip_sw_alert_handler_lpg_sleep_mode_alerts 27165003354283873752015413161443847323547788381357385158925041476652599997617 311
UVM_INFO @ 3662.844815 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [clkmgr_jitter_frequency_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected 1 test run
chip_sw_clkmgr_jitter_frequency 78169334042789858667053048872478894102725509812518260669833449065493537250645 346
UVM_INFO @ 4633.397530 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_rv_dm_access_after_wakeup_vseq.sv:93) [chip_sw_rv_dm_access_after_wakeup_vseq] Timed out waiting for device to wakeup from deep sleep. 1 test run
chip_sw_rv_dm_access_after_wakeup 101135889867812522680905208599162432139860486695675272139521758442795657359122 332
UVM_INFO @ 12944.840762 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_vseq.sv:660) [chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch 1 test run
chip_rv_dm_lc_disabled 34457151165707479281364813473450494560287809090581309099370864096808110010258 240
UVM_INFO @ 7161.743817 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:738) [chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (* [*] vs * [*]) Major alert did not match expectation. 1 test run
chip_sw_rv_core_ibex_lockstep_glitch 2356556450620189817829533857649670167255695595065586824696754941129423351116 325
UVM_INFO @ 3499.592828 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_power_idle_load_vseq.sv:24) [chip_sw_power_idle_load_vseq] timeout waiting for SW sync GPIO (*) 1 test run
chip_sw_power_idle_load 92224262830104304023022451377933928954060913134117154991977452667669451416914 321
UVM_INFO @ 16329.372018 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_power_sleep_load_vseq.sv:47) [chip_sw_power_sleep_load_vseq] timeout waiting for SW sync GPIO (*) 1 test run
chip_sw_power_sleep_load 54493999940473409453075687789670890418696176704389929729665764480549028198099 340
UVM_INFO @ 14961.661905 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/lib/testing/autogen/isr_testutils.c:41)] CHECK-fail: Only adc_ctrl IRQ * expected to fire. Actual IRQ state = * 1 test run
chip_sw_ast_clk_rst_inputs 47158572765425525741862403201573978924901227427353909310064764147216438708521 330
UVM_INFO @ 16486.211830 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (csr_utils_pkg.sv:619) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout chip_reg_block.spi_device.cmd_info_*.opcode (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=1) 1 test run
ate_bootstrap_flash_erase 4175298534943445686600771285028386735397575034924340118352384902687568548593 275
UVM_INFO @ 10010.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (jtag_rv_debugger.sv:784) [debugger] Index * appears to be out of bounds 1 test run
rom_e2e_jtag_debug_test_unlocked0 113578559633652747428710500511990842801412685615904353517012140629229323546538 321
UVM_INFO @ 5313.404795 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (jtag_rv_debugger.sv:613) [debugger] Check failed dcsr.cause == exp_debug_cause (* [*] vs * [*]) 1 test run
rom_e2e_jtag_debug_dev 36793020943027195855537191428217644835229508006707952907761034629661511455112 320
UVM_INFO @ 4404.445593 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred! 1 test run
rom_e2e_jtag_debug_rma 70119853869208465896878185924618320886978289286957750016154276563316453233921 333
UVM_INFO @ 15758.346286 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '$stable(key_data_i)' 1 test run
rom_keymgr_functest 82818049143417081604455597638228237143534842126468832489774010032232893779583 330
UVM_ERROR @ 5054.955320 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M
UVM_INFO @ 5054.955320 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---