Simulation Results: clkmgr

 
11/08/2026 15:30:30 DVSim: v1.50.1 sha: 14c137f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 92.94 %
  • code
  • 97.98 %
  • assert
  • 94.92 %
  • func
  • 85.93 %
  • line
  • 98.93 %
  • branch
  • 98.59 %
  • cond
  • 93.20 %
  • toggle
  • 99.19 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
91.67%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 0.790s 39.586us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 0.690s 15.322us 1 1 100.00
csr_rw 1 1 100.00
clkmgr_csr_rw 0.790s 20.373us 1 1 100.00
csr_bit_bash 1 1 100.00
clkmgr_csr_bit_bash 5.360s 1361.521us 1 1 100.00
csr_aliasing 1 1 100.00
clkmgr_csr_aliasing 1.080s 41.004us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
clkmgr_csr_mem_rw_with_rand_reset 2.350s 709.824us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
clkmgr_csr_rw 0.790s 20.373us 1 1 100.00
clkmgr_csr_aliasing 1.080s 41.004us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 0.900s 37.869us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 0.710s 16.646us 1 1 100.00
extclk 1 1 100.00
clkmgr_extclk 0.900s 89.098us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 1.010s 75.088us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 0.790s 39.586us 1 1 100.00
frequency 1 1 100.00
clkmgr_frequency 1.380s 322.101us 1 1 100.00
frequency_timeout 1 1 100.00
clkmgr_frequency_timeout 5.500s 1959.908us 1 1 100.00
frequency_overflow 1 1 100.00
clkmgr_frequency 1.380s 322.101us 1 1 100.00
stress_all 1 1 100.00
clkmgr_stress_all 0.910s 114.987us 1 1 100.00
alert_test 1 1 100.00
clkmgr_alert_test 0.770s 18.216us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 2.670s 150.959us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 2.670s 150.959us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
clkmgr_csr_hw_reset 0.690s 15.322us 1 1 100.00
clkmgr_csr_rw 0.790s 20.373us 1 1 100.00
clkmgr_csr_aliasing 1.080s 41.004us 1 1 100.00
clkmgr_same_csr_outstanding 0.980s 71.245us 1 1 100.00
tl_d_partial_access 4 4 100.00
clkmgr_csr_hw_reset 0.690s 15.322us 1 1 100.00
clkmgr_csr_rw 0.790s 20.373us 1 1 100.00
clkmgr_csr_aliasing 1.080s 41.004us 1 1 100.00
clkmgr_same_csr_outstanding 0.980s 71.245us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 1 2 50.00
clkmgr_sec_cm 0.700s 4.599us 0 1 0.00
clkmgr_tl_intg_err 1.610s 67.704us 1 1 100.00
shadow_reg_update_error 1 1 100.00
clkmgr_shadow_reg_errors 1.200s 124.841us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
clkmgr_shadow_reg_errors 1.200s 124.841us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
clkmgr_shadow_reg_errors 1.200s 124.841us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
clkmgr_shadow_reg_errors 1.200s 124.841us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
clkmgr_shadow_reg_errors_with_csr_rw 3.330s 694.799us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
clkmgr_tl_intg_err 1.610s 67.704us 1 1 100.00
sec_cm_meas_clk_bkgn_chk 1 1 100.00
clkmgr_frequency 1.380s 322.101us 1 1 100.00
sec_cm_timeout_clk_bkgn_chk 1 1 100.00
clkmgr_frequency_timeout 5.500s 1959.908us 1 1 100.00
sec_cm_meas_config_shadow 1 1 100.00
clkmgr_shadow_reg_errors 1.200s 124.841us 1 1 100.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 1.120s 36.925us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
clkmgr_lc_ctrl_intersig_mubi 0.780s 22.895us 1 1 100.00
sec_cm_lc_ctrl_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_lc_clk_byp_req_intersig_mubi 0.910s 27.797us 1 1 100.00
sec_cm_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_clk_handshake_intersig_mubi 1.070s 93.542us 1 1 100.00
sec_cm_div_intersig_mubi 1 1 100.00
clkmgr_div_intersig_mubi 1.310s 294.160us 1 1 100.00
sec_cm_jitter_config_mubi 1 1 100.00
clkmgr_csr_rw 0.790s 20.373us 1 1 100.00
sec_cm_idle_ctr_redun 0 1 0.00
clkmgr_sec_cm 0.700s 4.599us 0 1 0.00
sec_cm_meas_config_regwen 1 1 100.00
clkmgr_csr_rw 0.790s 20.373us 1 1 100.00
sec_cm_clk_ctrl_config_regwen 1 1 100.00
clkmgr_csr_rw 0.790s 20.373us 1 1 100.00
prim_count_check 0 1 0.00
clkmgr_sec_cm 0.700s 4.599us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 1 1 100.00
clkmgr_regwen 1.130s 194.427us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
clkmgr_stress_all_with_rand_reset 39.710s 13242.650us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1047) virtual_sequencer [clkmgr_common_vseq] Expected alert (fatal_fault) did not fire in * cycles. 1 test run
clkmgr_sec_cm 23776431663196566712376981083113758541756243827414718751826725340714836589494 80
UVM_INFO @ 4599468 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---