Simulation Results: csrng

 
11/08/2026 15:30:30 DVSim: v1.50.1 sha: 14c137f json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 86.84 %
  • code
  • 92.20 %
  • assert
  • 93.89 %
  • func
  • 74.44 %
  • block
  • 96.82 %
  • line
  • 97.62 %
  • branch
  • 92.09 %
  • toggle
  • 93.37 %
  • FSM
  • 85.71 %
Validation stages
V1
100.00%
V2
100.00%
V2S
87.50%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
csrng_smoke 2.000s 19.748us 1 1 100.00
csr_hw_reset 1 1 100.00
csrng_csr_hw_reset 2.000s 74.120us 1 1 100.00
csr_rw 1 1 100.00
csrng_csr_rw 2.000s 58.495us 1 1 100.00
csr_bit_bash 1 1 100.00
csrng_csr_bit_bash 32.000s 1880.453us 1 1 100.00
csr_aliasing 1 1 100.00
csrng_csr_aliasing 3.000s 90.446us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
csrng_csr_mem_rw_with_rand_reset 3.000s 90.190us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
csrng_csr_rw 2.000s 58.495us 1 1 100.00
csrng_csr_aliasing 3.000s 90.446us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
interrupts 1 1 100.00
csrng_intr 11.000s 958.902us 1 1 100.00
alerts 1 1 100.00
csrng_alert 2.000s 68.331us 1 1 100.00
err 1 1 100.00
csrng_err 2.000s 38.300us 1 1 100.00
cmds 1 1 100.00
csrng_cmds 5.000s 216.170us 1 1 100.00
life cycle 1 1 100.00
csrng_cmds 5.000s 216.170us 1 1 100.00
stress_all 1 1 100.00
csrng_stress_all 120.000s 3357.523us 1 1 100.00
intr_test 1 1 100.00
csrng_intr_test 2.000s 17.005us 1 1 100.00
alert_test 1 1 100.00
csrng_alert_test 2.000s 27.992us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
csrng_tl_errors 6.000s 223.834us 1 1 100.00
tl_d_illegal_access 1 1 100.00
csrng_tl_errors 6.000s 223.834us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
csrng_csr_hw_reset 2.000s 74.120us 1 1 100.00
csrng_csr_rw 2.000s 58.495us 1 1 100.00
csrng_csr_aliasing 3.000s 90.446us 1 1 100.00
csrng_same_csr_outstanding 3.000s 56.111us 1 1 100.00
tl_d_partial_access 4 4 100.00
csrng_csr_hw_reset 2.000s 74.120us 1 1 100.00
csrng_csr_rw 2.000s 58.495us 1 1 100.00
csrng_csr_aliasing 3.000s 90.446us 1 1 100.00
csrng_same_csr_outstanding 3.000s 56.111us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
csrng_sec_cm 4.000s 216.149us 1 1 100.00
csrng_tl_intg_err 3.000s 173.368us 1 1 100.00
sec_cm_config_regwen 1 2 50.00
csrng_regwen 2.000s 20.483us 0 1 0.00
csrng_csr_rw 2.000s 58.495us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
csrng_alert 2.000s 68.331us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
csrng_stress_all 120.000s 3357.523us 1 1 100.00
sec_cm_main_sm_fsm_sparse 3 3 100.00
csrng_intr 11.000s 958.902us 1 1 100.00
csrng_err 2.000s 38.300us 1 1 100.00
csrng_sec_cm 4.000s 216.149us 1 1 100.00
sec_cm_cmd_stage_fsm_sparse 3 3 100.00
csrng_intr 11.000s 958.902us 1 1 100.00
csrng_err 2.000s 38.300us 1 1 100.00
csrng_sec_cm 4.000s 216.149us 1 1 100.00
sec_cm_ctr_drbg_fsm_sparse 3 3 100.00
csrng_intr 11.000s 958.902us 1 1 100.00
csrng_err 2.000s 38.300us 1 1 100.00
csrng_sec_cm 4.000s 216.149us 1 1 100.00
sec_cm_ctr_drbg_ctr_redun 3 3 100.00
csrng_intr 11.000s 958.902us 1 1 100.00
csrng_err 2.000s 38.300us 1 1 100.00
csrng_sec_cm 4.000s 216.149us 1 1 100.00
sec_cm_gen_cmd_ctr_redun 3 3 100.00
csrng_intr 11.000s 958.902us 1 1 100.00
csrng_err 2.000s 38.300us 1 1 100.00
csrng_sec_cm 4.000s 216.149us 1 1 100.00
sec_cm_ctrl_mubi 1 1 100.00
csrng_alert 2.000s 68.331us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
csrng_intr 11.000s 958.902us 1 1 100.00
csrng_err 2.000s 38.300us 1 1 100.00
sec_cm_constants_lc_gated 1 1 100.00
csrng_stress_all 120.000s 3357.523us 1 1 100.00
sec_cm_sw_genbits_bus_consistency 1 1 100.00
csrng_alert 2.000s 68.331us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
csrng_tl_intg_err 3.000s 173.368us 1 1 100.00
sec_cm_aes_cipher_fsm_sparse 3 3 100.00
csrng_intr 11.000s 958.902us 1 1 100.00
csrng_err 2.000s 38.300us 1 1 100.00
csrng_sec_cm 4.000s 216.149us 1 1 100.00
sec_cm_aes_cipher_fsm_redun 2 2 100.00
csrng_intr 11.000s 958.902us 1 1 100.00
csrng_err 2.000s 38.300us 1 1 100.00
sec_cm_aes_cipher_ctrl_sparse 2 2 100.00
csrng_intr 11.000s 958.902us 1 1 100.00
csrng_err 2.000s 38.300us 1 1 100.00
sec_cm_aes_cipher_fsm_local_esc 2 2 100.00
csrng_intr 11.000s 958.902us 1 1 100.00
csrng_err 2.000s 38.300us 1 1 100.00
sec_cm_aes_cipher_ctr_redun 3 3 100.00
csrng_intr 11.000s 958.902us 1 1 100.00
csrng_err 2.000s 38.300us 1 1 100.00
csrng_sec_cm 4.000s 216.149us 1 1 100.00
sec_cm_aes_cipher_data_reg_local_esc 2 2 100.00
csrng_intr 11.000s 958.902us 1 1 100.00
csrng_err 2.000s 38.300us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
csrng_stress_all_with_rand_reset 3602.049s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (csrng_regwen_vseq.sv:67) virtual_sequencer [csrng_regwen_vseq] Was unable to flip INT_STATE_READ_ENABLE 1 test run
csrng_regwen 74597422294420486136621267117885860320375877951552077165424264829849586487820 99
UVM_INFO @ 20483173 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes 1 test run
csrng_stress_all_with_rand_reset 4129679048255972332461463413188671642591454044584609789629780255689113080903 None