Simulation Results: edn/edn0

 
11/08/2026 15:30:30 DVSim: v1.50.1 sha: 14c137f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 88.15 %
  • code
  • 86.43 %
  • assert
  • 98.26 %
  • func
  • 79.76 %
  • line
  • 98.32 %
  • branch
  • 94.42 %
  • cond
  • 88.68 %
  • toggle
  • 92.14 %
  • FSM
  • 58.60 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 1.210s 49.361us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.810s 15.753us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 1.070s 15.474us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 2.700s 140.856us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 0.980s 50.571us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.170s 101.333us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 1.070s 15.474us 1 1 100.00
edn_csr_aliasing 0.980s 50.571us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.310s 59.439us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.310s 59.439us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.310s 59.439us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.880s 49.711us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.350s 87.364us 1 1 100.00
errs 1 1 100.00
edn_err 0.980s 38.336us 1 1 100.00
disable 2 2 100.00
edn_disable 0.870s 41.426us 1 1 100.00
edn_disable_auto_req_mode 0.910s 76.433us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 2.420s 167.212us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.780s 14.064us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.920s 23.481us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 3.260s 135.626us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 3.260s 135.626us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.810s 15.753us 1 1 100.00
edn_csr_rw 1.070s 15.474us 1 1 100.00
edn_csr_aliasing 0.980s 50.571us 1 1 100.00
edn_same_csr_outstanding 1.130s 23.431us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.810s 15.753us 1 1 100.00
edn_csr_rw 1.070s 15.474us 1 1 100.00
edn_csr_aliasing 0.980s 50.571us 1 1 100.00
edn_same_csr_outstanding 1.130s 23.431us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 3.560s 622.437us 1 1 100.00
edn_tl_intg_err 1.680s 67.896us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.930s 17.473us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.350s 87.364us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 3.560s 622.437us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 3.560s 622.437us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 3.560s 622.437us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 3.560s 622.437us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.350s 87.364us 1 1 100.00
edn_sec_cm 3.560s 622.437us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.350s 87.364us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.680s 67.896us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 21.370s 1480.722us 1 1 100.00