Simulation Results: edn/edn1

 
11/08/2026 15:30:30 DVSim: v1.50.1 sha: 14c137f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 84.01 %
  • code
  • 76.18 %
  • assert
  • 97.92 %
  • func
  • 77.94 %
  • line
  • 95.45 %
  • branch
  • 86.15 %
  • cond
  • 84.31 %
  • toggle
  • 86.59 %
  • FSM
  • 28.41 %
Validation stages
V1
100.00%
V2
92.86%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.770s 62.771us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.800s 64.907us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 1.050s 27.098us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 1.650s 47.863us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 0.920s 25.871us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.100s 27.002us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 1.050s 27.098us 1 1 100.00
edn_csr_aliasing 0.920s 25.871us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 0.890s 81.309us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 0.890s 81.309us 1 1 100.00
genbits 1 1 100.00
edn_genbits 0.890s 81.309us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.960s 38.169us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.250s 308.302us 1 1 100.00
errs 1 1 100.00
edn_err 0.980s 28.669us 1 1 100.00
disable 1 2 50.00
edn_disable 0.940s 34.578us 1 1 100.00
edn_disable_auto_req_mode 6.570s 500.000us 0 1 0.00
stress_all 1 1 100.00
edn_stress_all 2.730s 213.152us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.720s 120.683us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.830s 19.514us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 2.570s 235.937us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 2.570s 235.937us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.800s 64.907us 1 1 100.00
edn_csr_rw 1.050s 27.098us 1 1 100.00
edn_csr_aliasing 0.920s 25.871us 1 1 100.00
edn_same_csr_outstanding 0.950s 66.689us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.800s 64.907us 1 1 100.00
edn_csr_rw 1.050s 27.098us 1 1 100.00
edn_csr_aliasing 0.920s 25.871us 1 1 100.00
edn_same_csr_outstanding 0.950s 66.689us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 4.340s 956.848us 1 1 100.00
edn_tl_intg_err 1.230s 139.774us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.990s 28.355us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.250s 308.302us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 4.340s 956.848us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 4.340s 956.848us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 4.340s 956.848us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 4.340s 956.848us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.250s 308.302us 1 1 100.00
edn_sec_cm 4.340s 956.848us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.250s 308.302us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.230s 139.774us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 43.350s 3198.771us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 1 test run
edn_disable_auto_req_mode 64424192991773782504498196867863805183704115067064583026199178092886832135327 88
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---