Simulation Results: entropy_src/rng_4bits

 
11/08/2026 15:30:30 DVSim: v1.50.1 sha: 14c137f json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 73.87 %
  • code
  • 86.31 %
  • assert
  • 83.42 %
  • func
  • 51.89 %
  • block
  • 94.10 %
  • line
  • 96.84 %
  • branch
  • 85.76 %
  • toggle
  • 76.18 %
  • FSM
  • 86.46 %
Validation stages
V1
83.33%
V2
93.75%
V2S
85.71%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
entropy_src_smoke 2.000s 25.821us 1 1 100.00
csr_hw_reset 1 1 100.00
entropy_src_csr_hw_reset 2.000s 20.785us 1 1 100.00
csr_rw 1 1 100.00
entropy_src_csr_rw 1.000s 133.486us 1 1 100.00
csr_bit_bash 1 1 100.00
entropy_src_csr_bit_bash 12.000s 956.251us 1 1 100.00
csr_aliasing 1 1 100.00
entropy_src_csr_aliasing 3.000s 467.580us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
entropy_src_csr_mem_rw_with_rand_reset 1.000s 9.383us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
entropy_src_csr_rw 1.000s 133.486us 1 1 100.00
entropy_src_csr_aliasing 3.000s 467.580us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 2 3 66.67
entropy_src_smoke 2.000s 25.821us 1 1 100.00
entropy_src_rng 193.000s 14037.873us 1 1 100.00
entropy_src_fw_ov 97.000s 5634.300us 0 1 0.00
firmware_mode 0 1 0.00
entropy_src_fw_ov 97.000s 5634.300us 0 1 0.00
rng_mode 1 1 100.00
entropy_src_rng 193.000s 14037.873us 1 1 100.00
rng_max_rate 1 1 100.00
entropy_src_rng_max_rate 124.000s 14093.004us 1 1 100.00
health_checks 1 1 100.00
entropy_src_rng 193.000s 14037.873us 1 1 100.00
conditioning 1 1 100.00
entropy_src_rng 193.000s 14037.873us 1 1 100.00
interrupts 2 2 100.00
entropy_src_rng 193.000s 14037.873us 1 1 100.00
entropy_src_intr 2.000s 53.215us 1 1 100.00
alerts 2 2 100.00
entropy_src_rng 193.000s 14037.873us 1 1 100.00
entropy_src_functional_alerts 4.000s 926.010us 1 1 100.00
stress_all 1 1 100.00
entropy_src_stress_all 80.000s 14235.241us 1 1 100.00
functional_errors 1 1 100.00
entropy_src_functional_errors 2.000s 155.478us 1 1 100.00
firmware_ov_read_contiguous_data 1 1 100.00
entropy_src_fw_ov_contiguous 2.000s 172.726us 1 1 100.00
intr_test 1 1 100.00
entropy_src_intr_test 2.000s 19.075us 1 1 100.00
alert_test 1 1 100.00
entropy_src_alert_test 2.000s 47.916us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
entropy_src_tl_errors 4.000s 255.372us 1 1 100.00
tl_d_illegal_access 1 1 100.00
entropy_src_tl_errors 4.000s 255.372us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
entropy_src_csr_hw_reset 2.000s 20.785us 1 1 100.00
entropy_src_csr_rw 1.000s 133.486us 1 1 100.00
entropy_src_csr_aliasing 3.000s 467.580us 1 1 100.00
entropy_src_same_csr_outstanding 3.000s 242.813us 1 1 100.00
tl_d_partial_access 4 4 100.00
entropy_src_csr_hw_reset 2.000s 20.785us 1 1 100.00
entropy_src_csr_rw 1.000s 133.486us 1 1 100.00
entropy_src_csr_aliasing 3.000s 467.580us 1 1 100.00
entropy_src_same_csr_outstanding 3.000s 242.813us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
entropy_src_sec_cm 3.000s 148.124us 1 1 100.00
entropy_src_tl_intg_err 3.000s 99.584us 1 1 100.00
sec_cm_config_regwen 2 2 100.00
entropy_src_rng 193.000s 14037.873us 1 1 100.00
entropy_src_cfg_regwen 1.000s 18.941us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
entropy_src_rng 193.000s 14037.873us 1 1 100.00
sec_cm_config_redun 1 1 100.00
entropy_src_rng 193.000s 14037.873us 1 1 100.00
sec_cm_intersig_mubi 1 2 50.00
entropy_src_rng 193.000s 14037.873us 1 1 100.00
entropy_src_fw_ov 97.000s 5634.300us 0 1 0.00
sec_cm_main_sm_fsm_sparse 2 2 100.00
entropy_src_functional_errors 2.000s 155.478us 1 1 100.00
entropy_src_sec_cm 3.000s 148.124us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 2 2 100.00
entropy_src_functional_errors 2.000s 155.478us 1 1 100.00
entropy_src_sec_cm 3.000s 148.124us 1 1 100.00
sec_cm_rng_bkgn_chk 1 1 100.00
entropy_src_rng 193.000s 14037.873us 1 1 100.00
sec_cm_fifo_ctr_redun 2 2 100.00
entropy_src_functional_errors 2.000s 155.478us 1 1 100.00
entropy_src_sec_cm 3.000s 148.124us 1 1 100.00
sec_cm_ctr_redun 2 2 100.00
entropy_src_functional_errors 2.000s 155.478us 1 1 100.00
entropy_src_sec_cm 3.000s 148.124us 1 1 100.00
sec_cm_ctr_local_esc 1 1 100.00
entropy_src_functional_errors 2.000s 155.478us 1 1 100.00
sec_cm_esfinal_rdata_bus_consistency 1 1 100.00
entropy_src_functional_alerts 4.000s 926.010us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
entropy_src_tl_intg_err 3.000s 99.584us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
external_health_tests 1 1 100.00
entropy_src_rng_with_xht_rsps 200.000s 14068.594us 1 1 100.00
stress_all_with_rand_reset 0 1 0.00
entropy_src_stress_all_with_rand_reset 4.000s 216.312us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (entropy_src_scoreboard.sv:1663) scoreboard [scoreboard] invalid csr: entropy_src_reg_block.alert_test 1 test run
entropy_src_stress_all_with_rand_reset 78737447328979420610460759226929327947929991545853060847961499089104065739083 115
UVM_INFO @ 216311969 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:354) scoreboard [scoreboard] alert recov_alert did not trigger max_delay:* 1 test run
entropy_src_fw_ov 57451581775526701693648870098136429922961146502643597699729510219487516781638 1171
UVM_INFO @ 5634299849 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (entropy_src_base_vseq.sv:83) virtual_sequencer [mirror] Failed to mirror adaptp_lo_total_fails 1 test run
entropy_src_csr_mem_rw_with_rand_reset 19888864684536879723699049251639249666617606856599647806377141659390258912767 113
UVM_INFO @ 9383366 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---