Simulation Results: flash_ctrl

 
11/08/2026 15:30:30 DVSim: v1.50.1 sha: 14c137f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.15 %
  • code
  • 93.24 %
  • assert
  • 96.94 %
  • func
  • 95.26 %
  • line
  • 95.95 %
  • branch
  • 97.01 %
  • cond
  • 93.66 %
  • toggle
  • 95.22 %
  • FSM
  • 84.35 %
Validation stages
V1
100.00%
V2
98.28%
V2S
91.67%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
flash_ctrl_smoke 62.730s 364.157us 1 1 100.00
smoke_hw 1 1 100.00
flash_ctrl_smoke_hw 14.470s 51.823us 1 1 100.00
csr_hw_reset 1 1 100.00
flash_ctrl_csr_hw_reset 15.030s 104.794us 1 1 100.00
csr_rw 1 1 100.00
flash_ctrl_csr_rw 7.730s 61.664us 1 1 100.00
csr_bit_bash 1 1 100.00
flash_ctrl_csr_bit_bash 45.170s 3926.217us 1 1 100.00
csr_aliasing 1 1 100.00
flash_ctrl_csr_aliasing 25.310s 3323.115us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
flash_ctrl_csr_mem_rw_with_rand_reset 12.300s 95.981us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
flash_ctrl_csr_rw 7.730s 61.664us 1 1 100.00
flash_ctrl_csr_aliasing 25.310s 3323.115us 1 1 100.00
mem_walk 1 1 100.00
flash_ctrl_mem_walk 7.950s 18.139us 1 1 100.00
mem_partial_access 1 1 100.00
flash_ctrl_mem_partial_access 10.790s 96.314us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sw_op 1 1 100.00
flash_ctrl_sw_op 15.410s 24.518us 1 1 100.00
host_read_direct 1 1 100.00
flash_ctrl_host_dir_rd 44.900s 311.920us 1 1 100.00
rma_hw_if 3 3 100.00
flash_ctrl_hw_rma 1054.960s 179531.820us 1 1 100.00
flash_ctrl_hw_rma_reset 522.960s 180208.943us 1 1 100.00
flash_ctrl_lcmgr_intg 10.460s 83.920us 1 1 100.00
host_controller_arb 1 1 100.00
flash_ctrl_host_ctrl_arb 1520.620s 258307.546us 1 1 100.00
erase_suspend 1 1 100.00
flash_ctrl_erase_suspend 181.880s 2062.360us 1 1 100.00
program_reset 1 1 100.00
flash_ctrl_prog_reset 5.990s 20.864us 1 1 100.00
full_memory_access 1 1 100.00
flash_ctrl_full_mem_access 2100.740s 55271.069us 1 1 100.00
rd_buff_eviction 1 1 100.00
flash_ctrl_rd_buff_evict 43.280s 1506.596us 1 1 100.00
rd_buff_eviction_w_ecc 3 3 100.00
flash_ctrl_rw_evict 17.550s 123.494us 1 1 100.00
flash_ctrl_rw_evict_all_en 14.180s 41.850us 1 1 100.00
flash_ctrl_re_evict 19.510s 206.269us 1 1 100.00
host_arb 1 1 100.00
flash_ctrl_phy_arb 67.860s 539.330us 1 1 100.00
host_interleave 1 1 100.00
flash_ctrl_phy_arb 67.860s 539.330us 1 1 100.00
memory_protection 1 1 100.00
flash_ctrl_mp_regions 293.500s 7684.592us 1 1 100.00
fetch_code 1 1 100.00
flash_ctrl_fetch_code 12.260s 132.547us 1 1 100.00
all_partitions 1 1 100.00
flash_ctrl_rand_ops 112.980s 121.946us 1 1 100.00
error_mp 1 1 100.00
flash_ctrl_error_mp 527.470s 19565.233us 1 1 100.00
error_prog_win 1 1 100.00
flash_ctrl_error_prog_win 399.420s 15821.911us 1 1 100.00
error_prog_type 1 1 100.00
flash_ctrl_error_prog_type 742.160s 744.881us 1 1 100.00
error_read_seed 1 1 100.00
flash_ctrl_hw_read_seed_err 8.620s 74.095us 1 1 100.00
read_write_overflow 1 1 100.00
flash_ctrl_oversize_error 133.210s 6120.120us 1 1 100.00
flash_ctrl_disable 1 1 100.00
flash_ctrl_disable 9.810s 38.603us 1 1 100.00
flash_ctrl_connect 1 1 100.00
flash_ctrl_connect 5.960s 19.862us 1 1 100.00
stress_all 1 1 100.00
flash_ctrl_stress_all 445.100s 1132.094us 1 1 100.00
secret_partition 2 2 100.00
flash_ctrl_hw_sec_otp 70.700s 13858.448us 1 1 100.00
flash_ctrl_otp_reset 65.590s 361.253us 1 1 100.00
isolation_partition 1 1 100.00
flash_ctrl_hw_rma 1054.960s 179531.820us 1 1 100.00
interrupts 3 4 75.00
flash_ctrl_intr_rd 132.470s 4258.737us 1 1 100.00
flash_ctrl_intr_wr 58.390s 17343.059us 1 1 100.00
flash_ctrl_intr_rd_slow_flash 145.930s 17870.987us 1 1 100.00
flash_ctrl_intr_wr_slow_flash 3603.776s 0.000us 0 1 0.00
invalid_op 1 1 100.00
flash_ctrl_invalid_op 49.120s 954.922us 1 1 100.00
mid_op_rst 1 1 100.00
flash_ctrl_mid_op_rst 35.820s 1218.178us 1 1 100.00
double_bit_err 5 5 100.00
flash_ctrl_read_word_sweep_derr 14.730s 120.602us 1 1 100.00
flash_ctrl_ro_derr 98.810s 698.348us 1 1 100.00
flash_ctrl_rw_derr 126.060s 6424.844us 1 1 100.00
flash_ctrl_derr_detect 98.790s 5796.040us 1 1 100.00
flash_ctrl_integrity 411.030s 15094.051us 1 1 100.00
single_bit_err 3 3 100.00
flash_ctrl_read_word_sweep_serr 11.500s 163.274us 1 1 100.00
flash_ctrl_ro_serr 86.160s 4750.472us 1 1 100.00
flash_ctrl_rw_serr 104.170s 911.596us 1 1 100.00
singlebit_err_counter 1 1 100.00
flash_ctrl_serr_counter 53.350s 5927.614us 1 1 100.00
singlebit_err_address 1 1 100.00
flash_ctrl_serr_address 40.260s 721.977us 1 1 100.00
scramble 5 5 100.00
flash_ctrl_wo 102.190s 2370.264us 1 1 100.00
flash_ctrl_write_word_sweep 7.230s 43.117us 1 1 100.00
flash_ctrl_read_word_sweep 8.510s 170.416us 1 1 100.00
flash_ctrl_ro 86.930s 1446.146us 1 1 100.00
flash_ctrl_rw 381.540s 19363.209us 1 1 100.00
filesystem_support 1 1 100.00
flash_ctrl_fs_sup 21.740s 3274.144us 1 1 100.00
rma_write_process_error 2 2 100.00
flash_ctrl_rma_err 513.410s 40374.108us 1 1 100.00
flash_ctrl_hw_prog_rma_wipe_err 97.070s 10039.461us 1 1 100.00
alert_test 1 1 100.00
flash_ctrl_alert_test 6.880s 68.914us 1 1 100.00
intr_test 1 1 100.00
flash_ctrl_intr_test 10.950s 31.946us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
flash_ctrl_tl_errors 9.220s 49.525us 1 1 100.00
tl_d_illegal_access 1 1 100.00
flash_ctrl_tl_errors 9.220s 49.525us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
flash_ctrl_csr_hw_reset 15.030s 104.794us 1 1 100.00
flash_ctrl_csr_rw 7.730s 61.664us 1 1 100.00
flash_ctrl_csr_aliasing 25.310s 3323.115us 1 1 100.00
flash_ctrl_same_csr_outstanding 19.550s 241.712us 1 1 100.00
tl_d_partial_access 4 4 100.00
flash_ctrl_csr_hw_reset 15.030s 104.794us 1 1 100.00
flash_ctrl_csr_rw 7.730s 61.664us 1 1 100.00
flash_ctrl_csr_aliasing 25.310s 3323.115us 1 1 100.00
flash_ctrl_same_csr_outstanding 19.550s 241.712us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
flash_ctrl_shadow_reg_errors 25.920s 26.708us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
flash_ctrl_shadow_reg_errors 25.920s 26.708us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
flash_ctrl_shadow_reg_errors 25.920s 26.708us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
flash_ctrl_shadow_reg_errors 25.920s 26.708us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
flash_ctrl_shadow_reg_errors_with_csr_rw 20.590s 54.593us 1 1 100.00
tl_intg_err 2 2 100.00
flash_ctrl_sec_cm 1747.600s 7477.689us 1 1 100.00
flash_ctrl_tl_intg_err 306.570s 829.681us 1 1 100.00
sec_cm_reg_bus_integrity 1 1 100.00
flash_ctrl_tl_intg_err 306.570s 829.681us 1 1 100.00
sec_cm_host_bus_integrity 1 1 100.00
flash_ctrl_tl_intg_err 306.570s 829.681us 1 1 100.00
sec_cm_mem_bus_integrity 2 2 100.00
flash_ctrl_rd_intg 16.660s 72.992us 1 1 100.00
flash_ctrl_wr_intg 63.920s 181.568us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
flash_ctrl_smoke 62.730s 364.157us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 4 4 100.00
flash_ctrl_otp_reset 65.590s 361.253us 1 1 100.00
flash_ctrl_disable 9.810s 38.603us 1 1 100.00
flash_ctrl_sec_info_access 41.240s 789.314us 1 1 100.00
flash_ctrl_connect 5.960s 19.862us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
flash_ctrl_config_regwen 6.200s 32.956us 1 1 100.00
sec_cm_data_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 7.730s 61.664us 1 1 100.00
sec_cm_data_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 25.920s 26.708us 1 1 100.00
sec_cm_info_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 7.730s 61.664us 1 1 100.00
sec_cm_info_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 25.920s 26.708us 1 1 100.00
sec_cm_bank_config_regwen 1 1 100.00
flash_ctrl_csr_rw 7.730s 61.664us 1 1 100.00
sec_cm_bank_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 25.920s 26.708us 1 1 100.00
sec_cm_mem_ctrl_global_esc 1 1 100.00
flash_ctrl_disable 9.810s 38.603us 1 1 100.00
sec_cm_mem_ctrl_local_esc 2 2 100.00
flash_ctrl_rd_intg 16.660s 72.992us 1 1 100.00
flash_ctrl_access_after_disable 6.680s 68.275us 1 1 100.00
sec_cm_mem_addr_infection 1 1 100.00
flash_ctrl_host_addr_infection 14.560s 28.506us 1 1 100.00
sec_cm_mem_disable_config_mubi 1 1 100.00
flash_ctrl_disable 9.810s 38.603us 1 1 100.00
sec_cm_exec_config_redun 1 1 100.00
flash_ctrl_fetch_code 12.260s 132.547us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
flash_ctrl_rw 381.540s 19363.209us 1 1 100.00
sec_cm_mem_integrity 3 3 100.00
flash_ctrl_rw_serr 104.170s 911.596us 1 1 100.00
flash_ctrl_rw_derr 126.060s 6424.844us 1 1 100.00
flash_ctrl_integrity 411.030s 15094.051us 1 1 100.00
sec_cm_rma_entry_mem_sec_wipe 1 1 100.00
flash_ctrl_hw_rma 1054.960s 179531.820us 1 1 100.00
sec_cm_ctrl_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1747.600s 7477.689us 1 1 100.00
sec_cm_phy_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1747.600s 7477.689us 1 1 100.00
sec_cm_phy_prog_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1747.600s 7477.689us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
flash_ctrl_sec_cm 1747.600s 7477.689us 1 1 100.00
sec_cm_phy_arbiter_ctrl_redun 1 1 100.00
flash_ctrl_phy_arb_redun 9.650s 857.265us 1 1 100.00
sec_cm_phy_host_grant_ctrl_consistency 0 1 0.00
flash_ctrl_phy_host_grant_err 8.850s 21.801us 0 1 0.00
sec_cm_phy_ack_ctrl_consistency 0 1 0.00
flash_ctrl_phy_ack_consistency 8.410s 16.963us 0 1 0.00
sec_cm_fifo_ctr_redun 1 1 100.00
flash_ctrl_sec_cm 1747.600s 7477.689us 1 1 100.00
sec_cm_mem_tl_lc_gate_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1747.600s 7477.689us 1 1 100.00
sec_cm_prog_tl_lc_gate_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1747.600s 7477.689us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
asymmetric_read_path 1 1 100.00
flash_ctrl_rd_ooo 21.840s 118.945us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
flash_ctrl_basic_rw 446.180s 4093.524us 1 1 100.00

Error Messages

   Test seed line log context
Job timed out after * minutes 1 test run
flash_ctrl_intr_wr_slow_flash 38510716838678192093061287179179765126053153866459237456552185831006920172814 None
Offending '(!$isunknown((alert_tx.alert_p ^ alert_tx.alert_n)))' 1 test run
flash_ctrl_phy_host_grant_err 17768134661463130882532394765772451787186300763749877337318206936448013043379 125
UVM_ERROR @ 21800.9 ns: (alert_esc_if.sv:211) [ASSERT FAILED] AlertKnown_A
UVM_INFO @ 21800.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (*) != exp (*) 1 test run
flash_ctrl_phy_ack_consistency 856534557218761697587300988998189238712443172216004308599141680458193140066 109
UVM_INFO @ 16962.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---