Simulation Results: hmac

 
11/08/2026 15:30:30 DVSim: v1.50.1 sha: 14c137f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 80.02 %
  • code
  • 97.70 %
  • assert
  • 97.60 %
  • func
  • 44.77 %
  • line
  • 99.59 %
  • branch
  • 98.84 %
  • cond
  • 95.96 %
  • toggle
  • 100.00 %
  • FSM
  • 94.12 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 4.780s 2114.977us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 1.100s 19.569us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 0.790s 21.006us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 4.650s 2718.159us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 5.470s 152.618us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 144.050s 27344.371us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 0.790s 21.006us 1 1 100.00
hmac_csr_aliasing 5.470s 152.618us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 26.550s 2426.330us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 45.510s 1984.282us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 8.550s 236.447us 1 1 100.00
hmac_test_sha384_vectors 20.010s 651.054us 1 1 100.00
hmac_test_sha512_vectors 20.640s 651.423us 1 1 100.00
hmac_test_hmac256_vectors 6.990s 535.815us 1 1 100.00
hmac_test_hmac384_vectors 9.130s 363.748us 1 1 100.00
hmac_test_hmac512_vectors 11.510s 457.756us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 5.250s 4495.164us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 442.020s 36930.999us 1 1 100.00
error 1 1 100.00
hmac_error 1.040s 135.025us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 20.960s 4688.976us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 4.780s 2114.977us 1 1 100.00
hmac_long_msg 26.550s 2426.330us 1 1 100.00
hmac_back_pressure 45.510s 1984.282us 1 1 100.00
hmac_datapath_stress 442.020s 36930.999us 1 1 100.00
hmac_burst_wr 5.250s 4495.164us 1 1 100.00
hmac_stress_all 1103.520s 44250.734us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 4.780s 2114.977us 1 1 100.00
hmac_long_msg 26.550s 2426.330us 1 1 100.00
hmac_back_pressure 45.510s 1984.282us 1 1 100.00
hmac_datapath_stress 442.020s 36930.999us 1 1 100.00
hmac_wipe_secret 20.960s 4688.976us 1 1 100.00
hmac_test_sha256_vectors 8.550s 236.447us 1 1 100.00
hmac_test_sha384_vectors 20.010s 651.054us 1 1 100.00
hmac_test_sha512_vectors 20.640s 651.423us 1 1 100.00
hmac_test_hmac256_vectors 6.990s 535.815us 1 1 100.00
hmac_test_hmac384_vectors 9.130s 363.748us 1 1 100.00
hmac_test_hmac512_vectors 11.510s 457.756us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 4.780s 2114.977us 1 1 100.00
hmac_long_msg 26.550s 2426.330us 1 1 100.00
hmac_back_pressure 45.510s 1984.282us 1 1 100.00
hmac_datapath_stress 442.020s 36930.999us 1 1 100.00
hmac_burst_wr 5.250s 4495.164us 1 1 100.00
hmac_error 1.040s 135.025us 1 1 100.00
hmac_wipe_secret 20.960s 4688.976us 1 1 100.00
hmac_test_sha256_vectors 8.550s 236.447us 1 1 100.00
hmac_test_sha384_vectors 20.010s 651.054us 1 1 100.00
hmac_test_sha512_vectors 20.640s 651.423us 1 1 100.00
hmac_test_hmac256_vectors 6.990s 535.815us 1 1 100.00
hmac_test_hmac384_vectors 9.130s 363.748us 1 1 100.00
hmac_test_hmac512_vectors 11.510s 457.756us 1 1 100.00
hmac_stress_all 1103.520s 44250.734us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 1103.520s 44250.734us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 0.640s 17.146us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 0.650s 13.276us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 1.520s 45.973us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 1.520s 45.973us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 1.100s 19.569us 1 1 100.00
hmac_csr_rw 0.790s 21.006us 1 1 100.00
hmac_csr_aliasing 5.470s 152.618us 1 1 100.00
hmac_same_csr_outstanding 1.140s 119.745us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 1.100s 19.569us 1 1 100.00
hmac_csr_rw 0.790s 21.006us 1 1 100.00
hmac_csr_aliasing 5.470s 152.618us 1 1 100.00
hmac_same_csr_outstanding 1.140s 119.745us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 1.010s 137.774us 1 1 100.00
hmac_tl_intg_err 2.790s 490.325us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 2.790s 490.325us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 4.780s 2114.977us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 3.140s 414.977us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 238.300s 61382.720us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 0.920s 55.862us 1 1 100.00