Simulation Results

Simulation Results: i2c

11/08/2026 15:30:30 DVSim: v1.50.1 sha: 14c137f json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
87.00 %

code
78.98 %

assert
97.25 %

func
84.78 %

line
96.91 %

branch
93.04 %

cond
86.85 %

toggle
74.04 %

FSM
44.05 %

Validation stages

V1		100.00%
V2		90.24%
V2S		100.00%
V3		0.00%

7/7 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_smoke				1	1	100.00
	i2c_host_smoke	35.880s	23483.395us	1	1	100.00
target_smoke				1	1	100.00
	i2c_target_smoke	5.600s	4568.956us	1	1	100.00
csr_hw_reset				1	1	100.00
	i2c_csr_hw_reset	0.960s	53.515us	1	1	100.00
csr_rw				1	1	100.00
	i2c_csr_rw	0.670s	18.862us	1	1	100.00
csr_bit_bash				1	1	100.00
	i2c_csr_bit_bash	4.120s	719.694us	1	1	100.00
csr_aliasing				1	1	100.00
	i2c_csr_aliasing	1.640s	115.354us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	i2c_csr_mem_rw_with_rand_reset	0.750s	75.431us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	i2c_csr_rw	0.670s	18.862us	1	1	100.00
	i2c_csr_aliasing	1.640s	115.354us	1	1	100.00

37/41 passed

90.24 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_error_intr				0	1	0.00
	i2c_host_error_intr	2.840s	224.939us	0	1	0.00
host_stress_all				1	1	100.00
	i2c_host_stress_all	273.140s	49873.974us	1	1	100.00
host_maxperf				1	1	100.00
	i2c_host_perf	67.760s	18557.287us	1	1	100.00
host_override				1	1	100.00
	i2c_host_override	0.740s	27.935us	1	1	100.00
host_fifo_watermark				1	1	100.00
	i2c_host_fifo_watermark	80.420s	38187.133us	1	1	100.00
host_fifo_overflow				1	1	100.00
	i2c_host_fifo_overflow	39.940s	2126.207us	1	1	100.00
host_fifo_reset				3	3	100.00
	i2c_host_fifo_reset_fmt	0.940s	101.753us	1	1	100.00
	i2c_host_fifo_fmt_empty	3.440s	273.643us	1	1	100.00
	i2c_host_fifo_reset_rx	4.330s	577.491us	1	1	100.00
host_fifo_full				1	1	100.00
	i2c_host_fifo_full	68.460s	5805.831us	1	1	100.00
host_timeout				1	1	100.00
	i2c_host_stretch_timeout	28.040s	925.530us	1	1	100.00
i2c_host_mode_toggle				0	1	0.00
	i2c_host_mode_toggle	0.630s	41.000us	0	1	0.00
target_glitch				0	1	0.00
	i2c_target_glitch	1.920s	2214.131us	0	1	0.00
target_stress_all				1	1	100.00
	i2c_target_stress_all	75.580s	26185.235us	1	1	100.00
target_maxperf				1	1	100.00
	i2c_target_perf	2.260s	5447.095us	1	1	100.00
target_fifo_empty				2	2	100.00
	i2c_target_stress_rd	12.950s	1132.617us	1	1	100.00
	i2c_target_intr_smoke	4.590s	5050.345us	1	1	100.00
target_fifo_reset				2	2	100.00
	i2c_target_fifo_reset_acq	1.010s	193.413us	1	1	100.00
	i2c_target_fifo_reset_tx	1.180s	234.187us	1	1	100.00
target_fifo_full				3	3	100.00
	i2c_target_stress_wr	12.630s	37745.402us	1	1	100.00
	i2c_target_stress_rd	12.950s	1132.617us	1	1	100.00
	i2c_target_intr_stress_wr	53.850s	16574.793us	1	1	100.00
target_timeout				1	1	100.00
	i2c_target_timeout	5.110s	2812.768us	1	1	100.00
target_clock_stretch				1	1	100.00
	i2c_target_stretch	6.460s	1592.580us	1	1	100.00
bad_address				1	1	100.00
	i2c_target_bad_addr	4.700s	6443.922us	1	1	100.00
target_mode_glitch				1	1	100.00
	i2c_target_hrst	2.130s	420.901us	1	1	100.00
target_fifo_watermark				2	2	100.00
	i2c_target_fifo_watermarks_acq	1.510s	1971.081us	1	1	100.00
	i2c_target_fifo_watermarks_tx	1.210s	122.540us	1	1	100.00
host_mode_config_perf				2	2	100.00
	i2c_host_perf	67.760s	18557.287us	1	1	100.00
	i2c_host_perf_precise	2.250s	352.170us	1	1	100.00
host_mode_clock_stretching				1	1	100.00
	i2c_host_stretch_timeout	28.040s	925.530us	1	1	100.00
target_mode_tx_stretch_ctrl				1	1	100.00
	i2c_target_tx_stretch_ctrl	11.540s	1186.995us	1	1	100.00
target_mode_nack_generation				2	3	66.67
	i2c_target_nack_acqfull	2.410s	1933.087us	1	1	100.00
	i2c_target_nack_acqfull_addr	1.930s	2192.257us	1	1	100.00
	i2c_target_nack_txstretch	1.210s	232.507us	0	1	0.00
host_mode_halt_on_nak				1	1	100.00
	i2c_host_may_nack	10.250s	465.981us	1	1	100.00
target_mode_smbus_maxlen				1	1	100.00
	i2c_target_smbus_maxlen	1.580s	1948.018us	1	1	100.00
alert_test				1	1	100.00
	i2c_alert_test	0.880s	16.297us	1	1	100.00
intr_test				1	1	100.00
	i2c_intr_test	0.790s	17.706us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	i2c_tl_errors	1.580s	160.709us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	i2c_tl_errors	1.580s	160.709us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	i2c_csr_hw_reset	0.960s	53.515us	1	1	100.00
	i2c_csr_rw	0.670s	18.862us	1	1	100.00
	i2c_csr_aliasing	1.640s	115.354us	1	1	100.00
	i2c_same_csr_outstanding	1.350s	403.274us	1	1	100.00
tl_d_partial_access				4	4	100.00
	i2c_csr_hw_reset	0.960s	53.515us	1	1	100.00
	i2c_csr_rw	0.670s	18.862us	1	1	100.00
	i2c_csr_aliasing	1.640s	115.354us	1	1	100.00
	i2c_same_csr_outstanding	1.350s	403.274us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	i2c_tl_intg_err	2.540s	131.255us	1	1	100.00
	i2c_sec_cm	0.890s	69.066us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	i2c_tl_intg_err	2.540s	131.255us	1	1	100.00

0/3 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Total
host_stress_all_with_rand_reset				1
	i2c_host_stress_all_with_rand_reset	10.710s	1690.795us	1
target_error_intr				1
	i2c_target_unexp_stop	0.990s	529.783us	1
target_stress_all_with_rand_reset				1
	i2c_target_stress_all_with_rand_reset	3.820s	169.961us	1

Error Messages

	Test	seed	line	log context
UVM_ERROR (cip_base_vseq.sv:1286) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.				2 test runs
	i2c_host_stress_all_with_rand_reset	72347219469320417512349475266405277090644621904838330592678382389712195884731	97	UVM_INFO @ 1690795121 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_target_stress_all_with_rand_reset	52754185477200772280900568583090791516195475169194206053714777690796018899024	83	UVM_INFO @ 169960971 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between				1 test run
	i2c_host_error_intr	84310350948365648230724193070286945719461055441433615821394242714231908981234	88	UVM_INFO @ 224939084 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between				1 test run
	i2c_target_glitch	35235566873784694396489549024199471834161730058327787546061283165530867468412	84	UVM_INFO @ 2214131268 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [] vs [*])				1 test run
	i2c_target_unexp_stop	35025057658167399440746657908710373134979841408378601462618965582111323119532	78	UVM_INFO @ 529782651 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:619) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout i2c_reg_block.status.hostidle (addr=, Comparison=CompareOpEq, exp_data=, call_count=3)				1 test run
	i2c_host_mode_toggle	40440741032967533779934410148783491869469937859968033054792744161103195676477	79	UVM_INFO @ 41000221 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_] Check failed obs == exp ( [] vs []) Regname: i2c_reg_block.target_nack_count reset value:				1 test run
	i2c_target_nack_txstretch	81094829551163104731196994882056295197276501759711573785594572477193142897941	78	UVM_INFO @ 232506811 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---