Simulation Results: lc_ctrl/volatile_unlock_disabled

 
11/08/2026 15:30:30 DVSim: v1.50.1 sha: 14c137f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.73 %
  • code
  • 83.76 %
  • assert
  • 94.69 %
  • func
  • 93.73 %
  • line
  • 97.20 %
  • branch
  • 93.70 %
  • cond
  • 79.51 %
  • toggle
  • 84.82 %
  • FSM
  • 63.55 %
Validation stages
V1
100.00%
V2
96.67%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 2.100s 420.742us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 0.880s 42.721us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.780s 13.341us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.180s 65.612us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 0.950s 17.611us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.000s 28.547us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.780s 13.341us 1 1 100.00
lc_ctrl_csr_aliasing 0.950s 17.611us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 1.850s 54.512us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 4.610s 1289.443us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.940s 42.192us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 2.330s 191.546us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 8.280s 1547.596us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 6.810s 571.720us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 8.280s 1547.596us 1 1 100.00
lc_ctrl_prog_failure 2.330s 191.546us 1 1 100.00
lc_ctrl_errors 6.810s 571.720us 1 1 100.00
lc_ctrl_security_escalation 5.210s 788.131us 1 1 100.00
lc_ctrl_jtag_state_failure 15.250s 4279.152us 1 1 100.00
lc_ctrl_jtag_prog_failure 7.290s 2859.034us 1 1 100.00
lc_ctrl_jtag_errors 16.880s 2927.073us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 1.490s 81.169us 1 1 100.00
lc_ctrl_jtag_state_post_trans 8.900s 376.957us 1 1 100.00
lc_ctrl_jtag_prog_failure 7.290s 2859.034us 1 1 100.00
lc_ctrl_jtag_errors 16.880s 2927.073us 1 1 100.00
lc_ctrl_jtag_access 2.720s 236.368us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 9.680s 1588.156us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 1.730s 93.955us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.170s 190.770us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 6.930s 932.661us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 2.340s 619.323us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.300s 257.768us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 1.110s 57.506us 1 1 100.00
lc_ctrl_jtag_alert_test 1.090s 224.660us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 2.340s 525.084us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.790s 15.009us 1 1 100.00
stress_all 0 1 0.00
lc_ctrl_stress_all 6.680s 265.726us 0 1 0.00
alert_test 1 1 100.00
lc_ctrl_alert_test 0.880s 79.206us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 2.240s 414.862us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 2.240s 414.862us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.880s 42.721us 1 1 100.00
lc_ctrl_csr_rw 0.780s 13.341us 1 1 100.00
lc_ctrl_csr_aliasing 0.950s 17.611us 1 1 100.00
lc_ctrl_same_csr_outstanding 0.940s 32.574us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.880s 42.721us 1 1 100.00
lc_ctrl_csr_rw 0.780s 13.341us 1 1 100.00
lc_ctrl_csr_aliasing 0.950s 17.611us 1 1 100.00
lc_ctrl_same_csr_outstanding 0.940s 32.574us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 6.190s 482.885us 1 1 100.00
lc_ctrl_tl_intg_err 1.520s 99.573us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.520s 99.573us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 4.610s 1289.443us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 8.280s 1547.596us 1 1 100.00
lc_ctrl_sec_cm 6.190s 482.885us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 8.280s 1547.596us 1 1 100.00
lc_ctrl_sec_cm 6.190s 482.885us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 8.280s 1547.596us 1 1 100.00
lc_ctrl_sec_cm 6.190s 482.885us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 8.280s 1547.596us 1 1 100.00
lc_ctrl_sec_cm 6.190s 482.885us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 8.280s 1547.596us 1 1 100.00
lc_ctrl_sec_cm 6.190s 482.885us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 8.280s 1547.596us 1 1 100.00
lc_ctrl_sec_cm 6.190s 482.885us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 8.280s 1547.596us 1 1 100.00
lc_ctrl_sec_cm 6.190s 482.885us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 8.280s 1547.596us 1 1 100.00
lc_ctrl_sec_cm 6.190s 482.885us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 5.210s 788.131us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 1.850s 54.512us 1 1 100.00
lc_ctrl_jtag_state_post_trans 8.900s 376.957us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.800s 1594.206us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.800s 1594.206us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 5.620s 295.564us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.970s 1621.121us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.970s 1621.121us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
lc_ctrl_stress_all_with_rand_reset 24.330s 24567.927us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (* [*] vs * [*]) 1 test run
lc_ctrl_stress_all 17634671044272143693725973372914910548832785728662846737121685935694712231278 3086
UVM_INFO @ 265725938 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---