Simulation Results: lc_ctrl/volatile_unlock_enabled

 
11/08/2026 15:30:30 DVSim: v1.50.1 sha: 14c137f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.57 %
  • code
  • 84.00 %
  • assert
  • 94.69 %
  • func
  • 93.01 %
  • line
  • 97.26 %
  • branch
  • 93.80 %
  • cond
  • 79.20 %
  • toggle
  • 86.21 %
  • FSM
  • 63.55 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.580s 103.805us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 0.950s 64.944us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 1.060s 28.576us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.670s 381.637us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.170s 167.175us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 0.930s 18.120us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 1.060s 28.576us 1 1 100.00
lc_ctrl_csr_aliasing 1.170s 167.175us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 4.170s 452.696us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 9.420s 1359.633us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.870s 14.167us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 1.990s 181.289us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 8.170s 690.815us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 4.450s 1805.230us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 8.170s 690.815us 1 1 100.00
lc_ctrl_prog_failure 1.990s 181.289us 1 1 100.00
lc_ctrl_errors 4.450s 1805.230us 1 1 100.00
lc_ctrl_security_escalation 4.370s 968.000us 1 1 100.00
lc_ctrl_jtag_state_failure 24.090s 11357.737us 1 1 100.00
lc_ctrl_jtag_prog_failure 6.240s 643.273us 1 1 100.00
lc_ctrl_jtag_errors 15.780s 1661.186us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 3.360s 1170.346us 1 1 100.00
lc_ctrl_jtag_state_post_trans 9.920s 1949.493us 1 1 100.00
lc_ctrl_jtag_prog_failure 6.240s 643.273us 1 1 100.00
lc_ctrl_jtag_errors 15.780s 1661.186us 1 1 100.00
lc_ctrl_jtag_access 4.110s 415.141us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 11.540s 4781.510us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 1.970s 688.472us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.270s 192.287us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 9.070s 6218.539us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 2.700s 2306.103us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.160s 47.453us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 1.370s 148.188us 1 1 100.00
lc_ctrl_jtag_alert_test 1.150s 90.181us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 4.190s 685.462us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.900s 16.139us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 55.090s 11473.569us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 0.790s 25.363us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 1.810s 296.523us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 1.810s 296.523us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.950s 64.944us 1 1 100.00
lc_ctrl_csr_rw 1.060s 28.576us 1 1 100.00
lc_ctrl_csr_aliasing 1.170s 167.175us 1 1 100.00
lc_ctrl_same_csr_outstanding 0.980s 53.701us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.950s 64.944us 1 1 100.00
lc_ctrl_csr_rw 1.060s 28.576us 1 1 100.00
lc_ctrl_csr_aliasing 1.170s 167.175us 1 1 100.00
lc_ctrl_same_csr_outstanding 0.980s 53.701us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 5.770s 449.164us 1 1 100.00
lc_ctrl_tl_intg_err 1.770s 275.870us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.770s 275.870us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 9.420s 1359.633us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 8.170s 690.815us 1 1 100.00
lc_ctrl_sec_cm 5.770s 449.164us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 8.170s 690.815us 1 1 100.00
lc_ctrl_sec_cm 5.770s 449.164us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 8.170s 690.815us 1 1 100.00
lc_ctrl_sec_cm 5.770s 449.164us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 8.170s 690.815us 1 1 100.00
lc_ctrl_sec_cm 5.770s 449.164us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 8.170s 690.815us 1 1 100.00
lc_ctrl_sec_cm 5.770s 449.164us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 8.170s 690.815us 1 1 100.00
lc_ctrl_sec_cm 5.770s 449.164us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 8.170s 690.815us 1 1 100.00
lc_ctrl_sec_cm 5.770s 449.164us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 8.170s 690.815us 1 1 100.00
lc_ctrl_sec_cm 5.770s 449.164us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 4.370s 968.000us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 4.170s 452.696us 1 1 100.00
lc_ctrl_jtag_state_post_trans 9.920s 1949.493us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.290s 1963.978us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.290s 1963.978us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 5.120s 908.609us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 3.870s 243.289us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 3.870s 243.289us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
lc_ctrl_stress_all_with_rand_reset 30.260s 2547.888us 1 1 100.00