Simulation Results: otp_ctrl

 
11/08/2026 15:30:30 DVSim: v1.50.1 sha: 14c137f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 82.61 %
  • code
  • 77.73 %
  • assert
  • 94.57 %
  • func
  • 75.53 %
  • line
  • 88.52 %
  • branch
  • 83.36 %
  • cond
  • 90.35 %
  • toggle
  • 83.04 %
  • FSM
  • 43.40 %
Validation stages
V1
100.00%
V2
95.00%
V2S
88.89%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 1.580s 827.519us 1 1 100.00
smoke 1 1 100.00
otp_ctrl_smoke 5.460s 830.449us 1 1 100.00
csr_hw_reset 1 1 100.00
otp_ctrl_csr_hw_reset 1.900s 101.902us 1 1 100.00
csr_rw 1 1 100.00
otp_ctrl_csr_rw 1.510s 177.648us 1 1 100.00
csr_bit_bash 1 1 100.00
otp_ctrl_csr_bit_bash 7.940s 583.766us 1 1 100.00
csr_aliasing 1 1 100.00
otp_ctrl_csr_aliasing 4.930s 718.451us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otp_ctrl_csr_mem_rw_with_rand_reset 2.080s 113.642us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otp_ctrl_csr_rw 1.510s 177.648us 1 1 100.00
otp_ctrl_csr_aliasing 4.930s 718.451us 1 1 100.00
mem_walk 1 1 100.00
otp_ctrl_mem_walk 1.210s 76.418us 1 1 100.00
mem_partial_access 1 1 100.00
otp_ctrl_mem_partial_access 1.130s 138.420us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 1 1 100.00
otp_ctrl_partition_walk 14.630s 912.054us 1 1 100.00
init_fail 1 1 100.00
otp_ctrl_init_fail 3.540s 583.642us 1 1 100.00
partition_check 1 2 50.00
otp_ctrl_background_chks 22.340s 11165.640us 1 1 100.00
otp_ctrl_check_fail 3.250s 240.848us 0 1 0.00
regwen_during_otp_init 1 1 100.00
otp_ctrl_regwen 3.000s 316.980us 1 1 100.00
partition_lock 1 1 100.00
otp_ctrl_dai_lock 12.780s 1172.602us 1 1 100.00
interface_key_check 1 1 100.00
otp_ctrl_parallel_key_req 12.740s 9323.975us 1 1 100.00
lc_interactions 2 2 100.00
otp_ctrl_parallel_lc_req 8.100s 1103.494us 1 1 100.00
otp_ctrl_parallel_lc_esc 6.170s 220.455us 1 1 100.00
otp_dai_errors 1 1 100.00
otp_ctrl_dai_errs 11.270s 1234.982us 1 1 100.00
otp_macro_errors 1 1 100.00
otp_ctrl_macro_errs 17.070s 2085.513us 1 1 100.00
test_access 1 1 100.00
otp_ctrl_test_access 53.170s 15792.338us 1 1 100.00
stress_all 1 1 100.00
otp_ctrl_stress_all 92.510s 18291.617us 1 1 100.00
intr_test 1 1 100.00
otp_ctrl_intr_test 1.200s 118.007us 1 1 100.00
alert_test 1 1 100.00
otp_ctrl_alert_test 2.000s 140.214us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otp_ctrl_tl_errors 3.670s 285.660us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otp_ctrl_tl_errors 3.670s 285.660us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otp_ctrl_csr_hw_reset 1.900s 101.902us 1 1 100.00
otp_ctrl_csr_rw 1.510s 177.648us 1 1 100.00
otp_ctrl_csr_aliasing 4.930s 718.451us 1 1 100.00
otp_ctrl_same_csr_outstanding 1.890s 170.464us 1 1 100.00
tl_d_partial_access 4 4 100.00
otp_ctrl_csr_hw_reset 1.900s 101.902us 1 1 100.00
otp_ctrl_csr_rw 1.510s 177.648us 1 1 100.00
otp_ctrl_csr_aliasing 4.930s 718.451us 1 1 100.00
otp_ctrl_same_csr_outstanding 1.890s 170.464us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 1 1 100.00
otp_ctrl_sec_cm 107.000s 13750.804us 1 1 100.00
tl_intg_err 2 2 100.00
otp_ctrl_sec_cm 107.000s 13750.804us 1 1 100.00
otp_ctrl_tl_intg_err 6.640s 712.759us 1 1 100.00
prim_count_check 1 1 100.00
otp_ctrl_sec_cm 107.000s 13750.804us 1 1 100.00
prim_fsm_check 1 1 100.00
otp_ctrl_sec_cm 107.000s 13750.804us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otp_ctrl_tl_intg_err 6.640s 712.759us 1 1 100.00
sec_cm_secret_mem_scramble 1 1 100.00
otp_ctrl_smoke 5.460s 830.449us 1 1 100.00
sec_cm_part_mem_digest 1 1 100.00
otp_ctrl_smoke 5.460s 830.449us 1 1 100.00
sec_cm_dai_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 107.000s 13750.804us 1 1 100.00
sec_cm_kdi_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 107.000s 13750.804us 1 1 100.00
sec_cm_lci_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 107.000s 13750.804us 1 1 100.00
sec_cm_part_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 107.000s 13750.804us 1 1 100.00
sec_cm_scrmbl_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 107.000s 13750.804us 1 1 100.00
sec_cm_timer_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 107.000s 13750.804us 1 1 100.00
sec_cm_dai_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 107.000s 13750.804us 1 1 100.00
sec_cm_kdi_seed_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 107.000s 13750.804us 1 1 100.00
sec_cm_kdi_entropy_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 107.000s 13750.804us 1 1 100.00
sec_cm_lci_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 107.000s 13750.804us 1 1 100.00
sec_cm_part_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 107.000s 13750.804us 1 1 100.00
sec_cm_scrmbl_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 107.000s 13750.804us 1 1 100.00
sec_cm_timer_integ_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 107.000s 13750.804us 1 1 100.00
sec_cm_timer_cnsty_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 107.000s 13750.804us 1 1 100.00
sec_cm_timer_lfsr_redun 1 1 100.00
otp_ctrl_sec_cm 107.000s 13750.804us 1 1 100.00
sec_cm_dai_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 6.170s 220.455us 1 1 100.00
otp_ctrl_sec_cm 107.000s 13750.804us 1 1 100.00
sec_cm_lci_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 6.170s 220.455us 1 1 100.00
sec_cm_kdi_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 6.170s 220.455us 1 1 100.00
sec_cm_part_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 6.170s 220.455us 1 1 100.00
otp_ctrl_macro_errs 17.070s 2085.513us 1 1 100.00
sec_cm_scrmbl_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 6.170s 220.455us 1 1 100.00
sec_cm_timer_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 6.170s 220.455us 1 1 100.00
otp_ctrl_sec_cm 107.000s 13750.804us 1 1 100.00
sec_cm_dai_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 6.170s 220.455us 1 1 100.00
otp_ctrl_sec_cm 107.000s 13750.804us 1 1 100.00
sec_cm_lci_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 6.170s 220.455us 1 1 100.00
sec_cm_kdi_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 6.170s 220.455us 1 1 100.00
sec_cm_part_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 6.170s 220.455us 1 1 100.00
otp_ctrl_macro_errs 17.070s 2085.513us 1 1 100.00
sec_cm_scrmbl_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 6.170s 220.455us 1 1 100.00
sec_cm_timer_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 6.170s 220.455us 1 1 100.00
otp_ctrl_sec_cm 107.000s 13750.804us 1 1 100.00
sec_cm_part_data_reg_integrity 1 1 100.00
otp_ctrl_init_fail 3.540s 583.642us 1 1 100.00
sec_cm_part_data_reg_bkgn_chk 0 1 0.00
otp_ctrl_check_fail 3.250s 240.848us 0 1 0.00
sec_cm_part_mem_regren 1 1 100.00
otp_ctrl_dai_lock 12.780s 1172.602us 1 1 100.00
sec_cm_part_mem_sw_unreadable 1 1 100.00
otp_ctrl_dai_lock 12.780s 1172.602us 1 1 100.00
sec_cm_part_mem_sw_unwritable 1 1 100.00
otp_ctrl_dai_lock 12.780s 1172.602us 1 1 100.00
sec_cm_lc_part_mem_sw_noaccess 1 1 100.00
otp_ctrl_dai_lock 12.780s 1172.602us 1 1 100.00
sec_cm_access_ctrl_mubi 1 1 100.00
otp_ctrl_dai_lock 12.780s 1172.602us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
otp_ctrl_smoke 5.460s 830.449us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
otp_ctrl_dai_lock 12.780s 1172.602us 1 1 100.00
sec_cm_test_bus_lc_gated 1 1 100.00
otp_ctrl_smoke 5.460s 830.449us 1 1 100.00
sec_cm_test_tl_lc_gate_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 107.000s 13750.804us 1 1 100.00
sec_cm_direct_access_config_regwen 1 1 100.00
otp_ctrl_regwen 3.000s 316.980us 1 1 100.00
sec_cm_check_trigger_config_regwen 1 1 100.00
otp_ctrl_smoke 5.460s 830.449us 1 1 100.00
sec_cm_check_config_regwen 1 1 100.00
otp_ctrl_smoke 5.460s 830.449us 1 1 100.00
sec_cm_macro_mem_integrity 1 1 100.00
otp_ctrl_macro_errs 17.070s 2085.513us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 1 1 100.00
otp_ctrl_low_freq_read 9.090s 3616.552us 1 1 100.00
stress_all_with_rand_reset 0 1 0.00
otp_ctrl_stress_all_with_rand_reset 55.000s 12838.495us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (otp_ctrl_scoreboard.sv:1208) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* 1 test run
otp_ctrl_check_fail 22094249718377373822076578612461201081447369392490801917936931808030253109581 2862
UVM_INFO @ 240848467 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:465) [otp_ctrl_common_vseq] wait timeout occurred! 1 test run
otp_ctrl_stress_all_with_rand_reset 46824429234659827064430650676866833094288508338176506437152993380049036663627 13134
UVM_INFO @ 12838495336 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---