Simulation Results: pwrmgr

 
11/08/2026 15:30:30 DVSim: v1.50.1 sha: 14c137f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.93 %
  • code
  • 91.24 %
  • assert
  • 98.69 %
  • func
  • 97.86 %
  • line
  • 99.09 %
  • branch
  • 96.18 %
  • cond
  • 95.76 %
  • toggle
  • 91.15 %
  • FSM
  • 74.00 %
Validation stages
V1
100.00%
V2
86.67%
V2S
100.00%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
pwrmgr_smoke 0.670s 29.774us 1 1 100.00
csr_hw_reset 1 1 100.00
pwrmgr_csr_hw_reset 0.650s 36.757us 1 1 100.00
csr_rw 1 1 100.00
pwrmgr_csr_rw 0.630s 37.841us 1 1 100.00
csr_bit_bash 1 1 100.00
pwrmgr_csr_bit_bash 1.340s 127.270us 1 1 100.00
csr_aliasing 1 1 100.00
pwrmgr_csr_aliasing 0.760s 134.999us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
pwrmgr_csr_mem_rw_with_rand_reset 0.780s 56.733us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
pwrmgr_csr_rw 0.630s 37.841us 1 1 100.00
pwrmgr_csr_aliasing 0.760s 134.999us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
wakeup 1 1 100.00
pwrmgr_wakeup 0.790s 341.415us 1 1 100.00
control_clks 1 1 100.00
pwrmgr_wakeup 0.790s 341.415us 1 1 100.00
aborted_low_power 2 2 100.00
pwrmgr_aborted_low_power 0.790s 88.938us 1 1 100.00
pwrmgr_lowpower_invalid 0.670s 40.560us 1 1 100.00
reset 0 2 0.00
pwrmgr_reset 2.100s 1000.000us 0 1 0.00
pwrmgr_reset_invalid 0.620s 39.900us 0 1 0.00
main_power_glitch_reset 0 1 0.00
pwrmgr_reset 2.100s 1000.000us 0 1 0.00
reset_wakeup_race 1 1 100.00
pwrmgr_wakeup_reset 0.960s 132.647us 1 1 100.00
lowpower_wakeup_race 1 1 100.00
pwrmgr_lowpower_wakeup_race 0.940s 276.347us 1 1 100.00
disable_rom_integrity_check 1 1 100.00
pwrmgr_disable_rom_integrity_check 0.840s 86.989us 1 1 100.00
stress_all 1 1 100.00
pwrmgr_stress_all 1.300s 691.605us 1 1 100.00
intr_test 1 1 100.00
pwrmgr_intr_test 0.620s 46.528us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
pwrmgr_tl_errors 1.950s 130.305us 1 1 100.00
tl_d_illegal_access 1 1 100.00
pwrmgr_tl_errors 1.950s 130.305us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
pwrmgr_csr_hw_reset 0.650s 36.757us 1 1 100.00
pwrmgr_csr_rw 0.630s 37.841us 1 1 100.00
pwrmgr_csr_aliasing 0.760s 134.999us 1 1 100.00
pwrmgr_same_csr_outstanding 0.890s 54.764us 1 1 100.00
tl_d_partial_access 4 4 100.00
pwrmgr_csr_hw_reset 0.650s 36.757us 1 1 100.00
pwrmgr_csr_rw 0.630s 37.841us 1 1 100.00
pwrmgr_csr_aliasing 0.760s 134.999us 1 1 100.00
pwrmgr_same_csr_outstanding 0.890s 54.764us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
pwrmgr_tl_intg_err 1.050s 228.315us 1 1 100.00
pwrmgr_sec_cm 1.470s 600.449us 1 1 100.00
prim_count_check 1 1 100.00
pwrmgr_sec_cm 1.470s 600.449us 1 1 100.00
prim_fsm_check 1 1 100.00
pwrmgr_sec_cm 1.470s 600.449us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
pwrmgr_tl_intg_err 1.050s 228.315us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_lc_ctrl_intersig_mubi 2.410s 824.110us 1 1 100.00
sec_cm_rom_ctrl_intersig_mubi 2 2 100.00
pwrmgr_wakeup_reset 0.960s 132.647us 1 1 100.00
pwrmgr_repeat_wakeup_reset 1.870s 1248.813us 1 1 100.00
sec_cm_rstmgr_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_rstmgr_intersig_mubi 0.800s 179.819us 1 1 100.00
sec_cm_esc_rx_clk_bkgn_chk 1 1 100.00
pwrmgr_esc_clk_rst_malfunc 0.650s 39.687us 1 1 100.00
sec_cm_esc_rx_clk_local_esc 1 1 100.00
pwrmgr_sec_cm 1.470s 600.449us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
pwrmgr_sec_cm 1.470s 600.449us 1 1 100.00
sec_cm_fsm_terminal 1 1 100.00
pwrmgr_sec_cm 1.470s 600.449us 1 1 100.00
sec_cm_ctrl_flow_global_esc 1 1 100.00
pwrmgr_global_esc 0.620s 110.078us 1 1 100.00
sec_cm_main_pd_rst_local_esc 1 1 100.00
pwrmgr_glitch 0.640s 34.515us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
pwrmgr_sec_cm_ctrl_config_regwen 0.960s 323.105us 1 1 100.00
sec_cm_wakeup_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.630s 37.841us 1 1 100.00
sec_cm_reset_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.630s 37.841us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
escalation_timeout 0 1 0.00
pwrmgr_escalation_timeout 0.810s 385.644us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
pwrmgr_stress_all_with_rand_reset 2.940s 1528.283us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 1 test run
pwrmgr_reset 70582313865411405216475264802077329718821081829217622607114702385636752059419 118
UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '((!clk_en) || status)' 1 test run
pwrmgr_escalation_timeout 113573050980386822420908570636893996546673895014700020368937989501437858364283 79
UVM_ERROR @ 385643507 ps: (clkmgr_pwrmgr_sva_if.sv:37) [ASSERT FAILED] StatusRise_A
UVM_INFO @ 385643507 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (pwrmgr_reset_invalid_vseq.sv:55) [pwrmgr_reset_invalid_vseq] Timed out waiting for state DVWaitNvmShutDown 1 test run
pwrmgr_reset_invalid 63034816304406547179812711411520584473679256314649382337710026710082458834031 79
UVM_INFO @ 39900155 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---