Simulation Results: rom_ctrl/32kb

 
11/08/2026 15:30:30 DVSim: v1.50.1 sha: 14c137f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.46 %
  • code
  • 98.22 %
  • assert
  • 96.81 %
  • func
  • 97.35 %
  • line
  • 99.20 %
  • branch
  • 98.91 %
  • cond
  • 97.92 %
  • toggle
  • 95.09 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
88.89%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 3.390s 767.476us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 3.800s 323.304us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 2.290s 64.845us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 1.990s 104.235us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 2.040s 76.771us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 2.360s 64.588us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 2.290s 64.845us 1 1 100.00
rom_ctrl_csr_aliasing 2.040s 76.771us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 1.730s 57.405us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 1.770s 104.892us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 0 1 0.00
rom_ctrl_max_throughput_chk 1.690s 4.362us 0 1 0.00
stress_all 1 1 100.00
rom_ctrl_stress_all 11.600s 755.411us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 3.660s 61.005us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 1.950s 51.080us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 4.240s 132.318us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 4.240s 132.318us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 3.800s 323.304us 1 1 100.00
rom_ctrl_csr_rw 2.290s 64.845us 1 1 100.00
rom_ctrl_csr_aliasing 2.040s 76.771us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.210s 75.310us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 3.800s 323.304us 1 1 100.00
rom_ctrl_csr_rw 2.290s 64.845us 1 1 100.00
rom_ctrl_csr_aliasing 2.040s 76.771us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.210s 75.310us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 62.270s 14100.636us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 13.250s 1105.565us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 200.160s 3051.417us 1 1 100.00
rom_ctrl_tl_intg_err 22.220s 369.080us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 200.160s 3051.417us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 200.160s 3051.417us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 62.270s 14100.636us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 62.270s 14100.636us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 62.270s 14100.636us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 62.270s 14100.636us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 62.270s 14100.636us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 200.160s 3051.417us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 200.160s 3051.417us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 3.390s 767.476us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 3.390s 767.476us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 3.390s 767.476us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 22.220s 369.080us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 62.270s 14100.636us 1 1 100.00
rom_ctrl_kmac_err_chk 3.660s 61.005us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 62.270s 14100.636us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 62.270s 14100.636us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 62.270s 14100.636us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 13.250s 1105.565us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 200.160s 3051.417us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 75.830s 1696.194us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (rom_ctrl_throughput_vseq.sv:52) [rom_ctrl_throughput_vseq] Check failed num_cycles == num_mem_reads + * (* [*] vs * [*]) 1 test run
rom_ctrl_max_throughput_chk 11942884129485944344707251572568145678684088792762199070538196612612204943282 79
UVM_INFO @ 4362072 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---