Simulation Results: rom_ctrl/64kb

 
11/08/2026 15:30:30 DVSim: v1.50.1 sha: 14c137f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 93.81 %
  • code
  • 88.23 %
  • assert
  • 97.53 %
  • func
  • 95.66 %
  • line
  • 98.53 %
  • branch
  • 98.54 %
  • cond
  • 95.69 %
  • toggle
  • 95.04 %
  • FSM
  • 53.33 %
Validation stages
V1
100.00%
V2
88.89%
V2S
83.33%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 6.830s 382.387us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 5.550s 58.259us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 3.030s 156.804us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 3.360s 147.233us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 3.390s 394.701us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 3.850s 193.252us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 3.030s 156.804us 1 1 100.00
rom_ctrl_csr_aliasing 3.390s 394.701us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 3.520s 77.163us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 3.350s 65.701us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 0 1 0.00
rom_ctrl_max_throughput_chk 3.020s 8.994us 0 1 0.00
stress_all 1 1 100.00
rom_ctrl_stress_all 7.860s 156.637us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 5.530s 58.648us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 3.510s 50.223us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 4.640s 116.366us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 4.640s 116.366us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 5.550s 58.259us 1 1 100.00
rom_ctrl_csr_rw 3.030s 156.804us 1 1 100.00
rom_ctrl_csr_aliasing 3.390s 394.701us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.280s 108.337us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 5.550s 58.259us 1 1 100.00
rom_ctrl_csr_rw 3.030s 156.804us 1 1 100.00
rom_ctrl_csr_aliasing 3.390s 394.701us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.280s 108.337us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 14.780s 45.182us 0 1 0.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 15.000s 247.590us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 461.930s 445.810us 1 1 100.00
rom_ctrl_tl_intg_err 97.370s 643.671us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 461.930s 445.810us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 461.930s 445.810us 1 1 100.00
sec_cm_checker_ctr_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 14.780s 45.182us 0 1 0.00
sec_cm_checker_ctrl_flow_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 14.780s 45.182us 0 1 0.00
sec_cm_checker_fsm_local_esc 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 14.780s 45.182us 0 1 0.00
sec_cm_compare_ctrl_flow_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 14.780s 45.182us 0 1 0.00
sec_cm_compare_ctr_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 14.780s 45.182us 0 1 0.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 461.930s 445.810us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 461.930s 445.810us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 6.830s 382.387us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 6.830s 382.387us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 6.830s 382.387us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 97.370s 643.671us 1 1 100.00
sec_cm_bus_local_esc 1 2 50.00
rom_ctrl_corrupt_sig_fatal_chk 14.780s 45.182us 0 1 0.00
rom_ctrl_kmac_err_chk 5.530s 58.648us 1 1 100.00
sec_cm_mux_mubi 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 14.780s 45.182us 0 1 0.00
sec_cm_mux_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 14.780s 45.182us 0 1 0.00
sec_cm_ctrl_redun 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 14.780s 45.182us 0 1 0.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 15.000s 247.590us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 461.930s 445.810us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 102.650s 2244.776us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (rom_ctrl_throughput_vseq.sv:52) [rom_ctrl_throughput_vseq] Check failed num_cycles == num_mem_reads + * (* [*] vs * [*]) 1 test run
rom_ctrl_max_throughput_chk 87332475828236784185916637507579331478774059613749731928057258981726656058161 79
UVM_INFO @ 8993541 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:278) [rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.fsm_vif.get_fsm_state() == rom_ctrl_pkg::ReadingLow) 1 test run
rom_ctrl_corrupt_sig_fatal_chk 33058668795691087412628887805734999639102949065048439754497644159228917848694 80
UVM_INFO @ 45182129 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---