Simulation Results: rstmgr_cnsty_chk

 
11/08/2026 15:30:30 DVSim: v1.50.1 sha: 14c137f json Branch: master Tool: vcs [unknown]
Validation stages
unmapped
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 0 1 0.00
rstmgr_cnsty_chk_test 2.480s 9053.916us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (tb.sv:272) [reset_class] Check failed ((delta_cycles < -12) || (delta_cycles > -1) || (error_count == *)) 1 test run
rstmgr_cnsty_chk_test 90884997432458959976696274805839037311324407729465698786119328311011981824980 175
UVM_INFO @ 1784245753 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -11 total errors 0 / 16
UVM_INFO @ 1802005753 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -10 total errors 0 / 16
UVM_INFO @ 1819765753 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -9 total errors 0 / 16
UVM_INFO @ 1837525753 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -8 total errors 0 / 16
Job cancelled because all of its dependencies failed or were killed. 1 test run
rstmgr_cnsty_chk None None
Job cancelled because one of its dependencies failed or was killed. 1 test run
rstmgr_cnsty_chk None None