Simulation Results: rv_timer

 
11/08/2026 15:30:30 DVSim: v1.50.1 sha: 14c137f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 92.67 %
  • code
  • 94.03 %
  • assert
  • 98.09 %
  • func
  • 85.88 %
  • line
  • 100.00 %
  • branch
  • 100.00 %
  • cond
  • 98.46 %
  • toggle
  • 77.64 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
random 1 1 100.00
rv_timer_random 0.900s 432.421us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 0.650s 30.779us 1 1 100.00
csr_rw 1 1 100.00
rv_timer_csr_rw 0.650s 24.039us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 2.880s 1866.309us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 0.850s 71.577us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_timer_csr_mem_rw_with_rand_reset 1.110s 37.873us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_timer_csr_rw 0.650s 24.039us 1 1 100.00
rv_timer_csr_aliasing 0.850s 71.577us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 1 1 100.00
rv_timer_random_reset 0.570s 107.099us 1 1 100.00
disabled 1 1 100.00
rv_timer_disabled 0.710s 202.882us 1 1 100.00
cfg_update_on_fly 1 1 100.00
rv_timer_cfg_update_on_fly 362.400s 1441672.819us 1 1 100.00
no_interrupt_test 1 1 100.00
rv_timer_cfg_update_on_fly 362.400s 1441672.819us 1 1 100.00
stress 1 1 100.00
rv_timer_stress_all 0.890s 1888.628us 1 1 100.00
alert_test 1 1 100.00
rv_timer_alert_test 0.740s 17.531us 1 1 100.00
intr_test 1 1 100.00
rv_timer_intr_test 0.570s 35.321us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_timer_tl_errors 1.390s 191.959us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_timer_tl_errors 1.390s 191.959us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_timer_csr_hw_reset 0.650s 30.779us 1 1 100.00
rv_timer_csr_rw 0.650s 24.039us 1 1 100.00
rv_timer_csr_aliasing 0.850s 71.577us 1 1 100.00
rv_timer_same_csr_outstanding 0.630s 128.303us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_timer_csr_hw_reset 0.650s 30.779us 1 1 100.00
rv_timer_csr_rw 0.650s 24.039us 1 1 100.00
rv_timer_csr_aliasing 0.850s 71.577us 1 1 100.00
rv_timer_same_csr_outstanding 0.630s 128.303us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_timer_sec_cm 0.790s 357.686us 1 1 100.00
rv_timer_tl_intg_err 0.730s 145.413us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_timer_tl_intg_err 0.730s 145.413us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 0 1 0.00
rv_timer_min 1.220s 1791.833us 0 1 0.00
max_value 0 1 0.00
rv_timer_max 0.730s 170.993us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
rv_timer_stress_all_with_rand_reset 15.120s 1487.808us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * 1 test run
rv_timer_min 37749261267024656592926654044618413451165745791999995247539553732769823165171 77
UVM_INFO @ 1791832767 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) 1 test run
rv_timer_max 113542784286646756980277064196979737893113332266287816544141446480254499176237 75
UVM_INFO @ 170992547 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues 1 test run
rv_timer_stress_all_with_rand_reset 34361452078972802184204011189808158736557274121248409444603001932608541556966 171
UVM_INFO @ 1487807714 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---