Simulation Results: sram_ctrl/main

 
11/08/2026 15:30:30 DVSim: v1.50.1 sha: 14c137f json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 95.24 %
  • code
  • 95.67 %
  • assert
  • 97.69 %
  • func
  • 92.35 %
  • block
  • 96.02 %
  • line
  • 96.75 %
  • branch
  • 94.16 %
  • toggle
  • 91.79 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 3.000s 4265.962us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 2.000s 43.224us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 1.000s 79.877us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 2.000s 64.488us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 17.084us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 2.000s 352.514us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 1.000s 79.877us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 17.084us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 185.000s 6220.332us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 69.000s 37463.978us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 36.000s 31809.218us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 125.000s 3884.602us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 150.000s 17866.483us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 61.000s 49936.214us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 20.000s 7989.997us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 3.000s 370.106us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 6.000s 708.837us 1 1 100.00
sram_ctrl_partial_access_b2b 115.000s 5014.253us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 3.000s 679.039us 1 1 100.00
sram_ctrl_throughput_w_partial_write 4.000s 1337.430us 1 1 100.00
sram_ctrl_throughput_w_readback 4.000s 676.181us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 10.000s 3446.071us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 2.000s 1363.488us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 247.000s 13284.321us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 2.000s 33.719us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 3.000s 405.148us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 3.000s 405.148us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 2.000s 43.224us 1 1 100.00
sram_ctrl_csr_rw 1.000s 79.877us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 17.084us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 14.414us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 2.000s 43.224us 1 1 100.00
sram_ctrl_csr_rw 1.000s 79.877us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 17.084us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 14.414us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 22.000s 7259.550us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 3.000s 550.869us 1 1 100.00
sram_ctrl_tl_intg_err 3.000s 280.909us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 3.000s 550.869us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 3.000s 280.909us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 10.000s 3446.071us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 10.000s 3446.071us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 1.000s 79.877us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 3.000s 370.106us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 3.000s 370.106us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 3.000s 370.106us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 20.000s 7989.997us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 4.000s 3936.207us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 22.000s 7259.550us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 4.000s 697.147us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 3.000s 4265.962us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 3.000s 4265.962us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 3.000s 370.106us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 3.000s 550.869us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 20.000s 7989.997us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 3.000s 550.869us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 550.869us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 3.000s 4265.962us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 550.869us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 19.000s 1154.529us 1 1 100.00