Simulation Results: sysrst_ctrl

 
11/08/2026 15:30:30 DVSim: v1.50.1 sha: 14c137f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 81.74 %
  • code
  • 90.27 %
  • assert
  • 89.37 %
  • func
  • 65.59 %
  • line
  • 95.76 %
  • branch
  • 96.37 %
  • cond
  • 93.19 %
  • toggle
  • 100.00 %
  • FSM
  • 66.03 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sysrst_ctrl_smoke 1.220s 2139.940us 1 1 100.00
input_output_inverted 1 1 100.00
sysrst_ctrl_in_out_inverted 4.770s 2467.958us 1 1 100.00
combo_detect_ec_rst 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst 5.330s 2251.818us 1 1 100.00
combo_detect_ec_rst_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 2.990s 2511.113us 1 1 100.00
csr_hw_reset 1 1 100.00
sysrst_ctrl_csr_hw_reset 10.230s 6020.239us 1 1 100.00
csr_rw 1 1 100.00
sysrst_ctrl_csr_rw 2.340s 2079.489us 1 1 100.00
csr_bit_bash 1 1 100.00
sysrst_ctrl_csr_bit_bash 127.220s 75775.226us 1 1 100.00
csr_aliasing 1 1 100.00
sysrst_ctrl_csr_aliasing 3.860s 2633.429us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sysrst_ctrl_csr_mem_rw_with_rand_reset 2.800s 2117.437us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sysrst_ctrl_csr_rw 2.340s 2079.489us 1 1 100.00
sysrst_ctrl_csr_aliasing 3.860s 2633.429us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
combo_detect 1 1 100.00
sysrst_ctrl_combo_detect 41.000s 105137.042us 1 1 100.00
combo_detect_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_with_pre_cond 14.740s 58370.971us 1 1 100.00
auto_block_key_outputs 1 1 100.00
sysrst_ctrl_auto_blk_key_output 3.370s 3353.799us 1 1 100.00
keyboard_input_triggered_interrupt 1 1 100.00
sysrst_ctrl_edge_detect 3.420s 2932.957us 1 1 100.00
pin_output_keyboard_inversion_control 1 1 100.00
sysrst_ctrl_pin_override_test 3.100s 2517.248us 1 1 100.00
pin_input_value_accessibility 1 1 100.00
sysrst_ctrl_pin_access_test 1.330s 2135.238us 1 1 100.00
ec_power_on_reset 1 1 100.00
sysrst_ctrl_ec_pwr_on_rst 949.260s 1208185.204us 1 1 100.00
flash_write_protect_output 1 1 100.00
sysrst_ctrl_flash_wr_prot_out 2.550s 2630.130us 1 1 100.00
ultra_low_power_test 1 1 100.00
sysrst_ctrl_ultra_low_pwr 6.560s 4875.008us 1 1 100.00
sysrst_ctrl_feature_disable 1 1 100.00
sysrst_ctrl_feature_disable 31.260s 35555.152us 1 1 100.00
stress_all 1 1 100.00
sysrst_ctrl_stress_all 10.240s 12924.075us 1 1 100.00
alert_test 1 1 100.00
sysrst_ctrl_alert_test 1.680s 2045.492us 1 1 100.00
intr_test 1 1 100.00
sysrst_ctrl_intr_test 3.550s 2013.694us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sysrst_ctrl_tl_errors 4.070s 2042.240us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sysrst_ctrl_tl_errors 4.070s 2042.240us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 10.230s 6020.239us 1 1 100.00
sysrst_ctrl_csr_rw 2.340s 2079.489us 1 1 100.00
sysrst_ctrl_csr_aliasing 3.860s 2633.429us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 8.290s 4556.460us 1 1 100.00
tl_d_partial_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 10.230s 6020.239us 1 1 100.00
sysrst_ctrl_csr_rw 2.340s 2079.489us 1 1 100.00
sysrst_ctrl_csr_aliasing 3.860s 2633.429us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 8.290s 4556.460us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
sysrst_ctrl_sec_cm 10.490s 22098.812us 1 1 100.00
sysrst_ctrl_tl_intg_err 9.620s 22510.967us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sysrst_ctrl_tl_intg_err 9.620s 22510.967us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sysrst_ctrl_stress_all_with_rand_reset 6.260s 3016.161us 1 1 100.00