Simulation Results: uart

 
11/08/2026 15:30:30 DVSim: v1.50.1 sha: 14c137f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 83.07 %
  • code
  • 91.74 %
  • assert
  • 98.85 %
  • func
  • 58.62 %
  • line
  • 99.17 %
  • branch
  • 97.44 %
  • cond
  • 95.68 %
  • toggle
  • 74.67 %
Validation stages
V1
100.00%
V2
95.45%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
uart_smoke 1.770s 667.128us 1 1 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 0.790s 19.112us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 0.730s 17.644us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 1.320s 171.879us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 0.980s 55.231us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 1.110s 19.350us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 0.730s 17.644us 1 1 100.00
uart_csr_aliasing 0.980s 55.231us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 1 1 100.00
uart_tx_rx 31.240s 411472.920us 1 1 100.00
parity 2 2 100.00
uart_smoke 1.770s 667.128us 1 1 100.00
uart_tx_rx 31.240s 411472.920us 1 1 100.00
parity_error 2 2 100.00
uart_intr 15.410s 26440.479us 1 1 100.00
uart_rx_parity_err 17.030s 59140.809us 1 1 100.00
watermark 2 2 100.00
uart_tx_rx 31.240s 411472.920us 1 1 100.00
uart_intr 15.410s 26440.479us 1 1 100.00
fifo_full 1 1 100.00
uart_fifo_full 17.460s 33914.168us 1 1 100.00
fifo_overflow 1 1 100.00
uart_fifo_overflow 16.900s 19345.836us 1 1 100.00
fifo_reset 1 1 100.00
uart_fifo_reset 12.600s 14983.190us 1 1 100.00
rx_frame_err 1 1 100.00
uart_intr 15.410s 26440.479us 1 1 100.00
rx_break_err 1 1 100.00
uart_intr 15.410s 26440.479us 1 1 100.00
rx_timeout 1 1 100.00
uart_intr 15.410s 26440.479us 1 1 100.00
perf 1 1 100.00
uart_perf 145.280s 5499.550us 1 1 100.00
sys_loopback 1 1 100.00
uart_loopback 10.770s 7927.283us 1 1 100.00
line_loopback 1 1 100.00
uart_loopback 10.770s 7927.283us 1 1 100.00
rx_noise_filter 0 1 0.00
uart_noise_filter 5.880s 15961.849us 0 1 0.00
rx_start_bit_filter 1 1 100.00
uart_rx_start_bit_filter 30.820s 37021.132us 1 1 100.00
tx_overide 1 1 100.00
uart_tx_ovrd 1.750s 743.123us 1 1 100.00
rx_oversample 1 1 100.00
uart_rx_oversample 2.230s 3076.958us 1 1 100.00
long_b2b_transfer 1 1 100.00
uart_long_xfer_wo_dly 61.750s 91123.520us 1 1 100.00
stress_all 1 1 100.00
uart_stress_all 152.280s 289841.046us 1 1 100.00
alert_test 1 1 100.00
uart_alert_test 0.690s 20.067us 1 1 100.00
intr_test 1 1 100.00
uart_intr_test 0.670s 85.722us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 2.340s 511.712us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 2.340s 511.712us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 0.790s 19.112us 1 1 100.00
uart_csr_rw 0.730s 17.644us 1 1 100.00
uart_csr_aliasing 0.980s 55.231us 1 1 100.00
uart_same_csr_outstanding 0.740s 55.153us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 0.790s 19.112us 1 1 100.00
uart_csr_rw 0.730s 17.644us 1 1 100.00
uart_csr_aliasing 0.980s 55.231us 1 1 100.00
uart_same_csr_outstanding 0.740s 55.153us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
uart_sec_cm 1.040s 40.432us 1 1 100.00
uart_tl_intg_err 0.830s 306.866us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 0.830s 306.866us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
uart_stress_all_with_rand_reset 8.310s 12196.769us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uart_scoreboard.sv:393) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [*] vs * [*]) check rx_idle fail: rx_en = *, uart_rx_clk_pulses = * 1 test run
uart_noise_filter 54064889963638885839245759031355348303142410876605968756585522583598052329581 75
UVM_ERROR @ 11139616718 ps: (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
UVM_ERROR @ 12027741824 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
UVM_ERROR @ 12027741824 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 12027741824 ps: (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1