Simulation Results: adc_ctrl

 
12/08/2026 15:30:28 DVSim: v1.50.1 sha: 71b9f97 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 71.07 %
  • code
  • 97.91 %
  • assert
  • 96.60 %
  • func
  • 18.69 %
  • line
  • 99.05 %
  • branch
  • 98.51 %
  • cond
  • 94.71 %
  • toggle
  • 100.00 %
  • FSM
  • 97.30 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
adc_ctrl_smoke 2.500s 5866.326us 1 1 100.00
csr_hw_reset 1 1 100.00
adc_ctrl_csr_hw_reset 1.060s 1238.129us 1 1 100.00
csr_rw 1 1 100.00
adc_ctrl_csr_rw 1.100s 355.643us 1 1 100.00
csr_bit_bash 1 1 100.00
adc_ctrl_csr_bit_bash 12.930s 21216.833us 1 1 100.00
csr_aliasing 1 1 100.00
adc_ctrl_csr_aliasing 1.860s 1082.950us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
adc_ctrl_csr_mem_rw_with_rand_reset 1.090s 543.129us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
adc_ctrl_csr_rw 1.100s 355.643us 1 1 100.00
adc_ctrl_csr_aliasing 1.860s 1082.950us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
filters_polled 1 1 100.00
adc_ctrl_filters_polled 26.210s 37353.334us 1 1 100.00
filters_polled_fixed 1 1 100.00
adc_ctrl_filters_polled_fixed 6.590s 18231.530us 1 1 100.00
filters_interrupt 1 1 100.00
adc_ctrl_filters_interrupt 52.320s 34898.471us 1 1 100.00
filters_interrupt_fixed 1 1 100.00
adc_ctrl_filters_interrupt_fixed 80.200s 52820.946us 1 1 100.00
filters_wakeup 1 1 100.00
adc_ctrl_filters_wakeup 61.710s 45503.163us 1 1 100.00
filters_wakeup_fixed 1 1 100.00
adc_ctrl_filters_wakeup_fixed 84.420s 68636.317us 1 1 100.00
filters_both 1 1 100.00
adc_ctrl_filters_both 23.820s 73848.602us 1 1 100.00
clock_gating 1 1 100.00
adc_ctrl_clock_gating 8.520s 23396.532us 1 1 100.00
poweron_counter 1 1 100.00
adc_ctrl_poweron_counter 3.710s 4319.865us 1 1 100.00
lowpower_counter 1 1 100.00
adc_ctrl_lowpower_counter 40.950s 31539.772us 1 1 100.00
fsm_reset 1 1 100.00
adc_ctrl_fsm_reset 198.710s 141362.202us 1 1 100.00
stress_all 1 1 100.00
adc_ctrl_stress_all 26.790s 25883.696us 1 1 100.00
alert_test 1 1 100.00
adc_ctrl_alert_test 1.220s 416.350us 1 1 100.00
intr_test 1 1 100.00
adc_ctrl_intr_test 1.060s 353.152us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
adc_ctrl_tl_errors 0.930s 417.365us 1 1 100.00
tl_d_illegal_access 1 1 100.00
adc_ctrl_tl_errors 0.930s 417.365us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
adc_ctrl_csr_hw_reset 1.060s 1238.129us 1 1 100.00
adc_ctrl_csr_rw 1.100s 355.643us 1 1 100.00
adc_ctrl_csr_aliasing 1.860s 1082.950us 1 1 100.00
adc_ctrl_same_csr_outstanding 5.700s 2664.259us 1 1 100.00
tl_d_partial_access 4 4 100.00
adc_ctrl_csr_hw_reset 1.060s 1238.129us 1 1 100.00
adc_ctrl_csr_rw 1.100s 355.643us 1 1 100.00
adc_ctrl_csr_aliasing 1.860s 1082.950us 1 1 100.00
adc_ctrl_same_csr_outstanding 5.700s 2664.259us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
adc_ctrl_sec_cm 1.790s 8266.297us 1 1 100.00
adc_ctrl_tl_intg_err 11.820s 8030.997us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
adc_ctrl_tl_intg_err 11.820s 8030.997us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
adc_ctrl_stress_all_with_rand_reset 5.790s 14374.406us 1 1 100.00