Simulation Results: aes/masked

 
12/08/2026 15:30:28 DVSim: v1.50.1 sha: 71b9f97 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 88.08 %
  • code
  • 94.11 %
  • assert
  • 98.23 %
  • func
  • 71.89 %
  • block
  • 94.23 %
  • line
  • 95.82 %
  • branch
  • 87.09 %
  • toggle
  • 97.99 %
  • FSM
  • 95.56 %
Validation stages
V1
100.00%
V2
100.00%
V2S
93.75%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 92.195us 1 1 100.00
smoke 1 1 100.00
aes_smoke 4.000s 223.140us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 2.000s 53.383us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 1.000s 53.595us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 5.000s 255.909us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 2.000s 158.080us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 2.000s 83.700us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 1.000s 53.595us 1 1 100.00
aes_csr_aliasing 2.000s 158.080us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 4.000s 223.140us 1 1 100.00
aes_config_error 5.000s 225.757us 1 1 100.00
aes_stress 2.000s 117.513us 1 1 100.00
key_length 3 3 100.00
aes_smoke 4.000s 223.140us 1 1 100.00
aes_config_error 5.000s 225.757us 1 1 100.00
aes_stress 2.000s 117.513us 1 1 100.00
back2back 2 2 100.00
aes_stress 2.000s 117.513us 1 1 100.00
aes_b2b 11.000s 243.668us 1 1 100.00
backpressure 1 1 100.00
aes_stress 2.000s 117.513us 1 1 100.00
multi_message 4 4 100.00
aes_smoke 4.000s 223.140us 1 1 100.00
aes_config_error 5.000s 225.757us 1 1 100.00
aes_stress 2.000s 117.513us 1 1 100.00
aes_alert_reset 2.000s 76.214us 1 1 100.00
failure_test 3 3 100.00
aes_man_cfg_err 2.000s 80.531us 1 1 100.00
aes_config_error 5.000s 225.757us 1 1 100.00
aes_alert_reset 2.000s 76.214us 1 1 100.00
trigger_clear_test 1 1 100.00
aes_clear 5.000s 225.087us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 7.000s 484.172us 1 1 100.00
reset_recovery 1 1 100.00
aes_alert_reset 2.000s 76.214us 1 1 100.00
stress 1 1 100.00
aes_stress 2.000s 117.513us 1 1 100.00
sideload 2 2 100.00
aes_stress 2.000s 117.513us 1 1 100.00
aes_sideload 4.000s 259.382us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 3.000s 138.348us 1 1 100.00
stress_all 1 1 100.00
aes_stress_all 12.000s 285.165us 1 1 100.00
alert_test 1 1 100.00
aes_alert_test 2.000s 83.156us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 2.000s 74.552us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 2.000s 74.552us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 2.000s 53.383us 1 1 100.00
aes_csr_rw 1.000s 53.595us 1 1 100.00
aes_csr_aliasing 2.000s 158.080us 1 1 100.00
aes_same_csr_outstanding 2.000s 220.398us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 2.000s 53.383us 1 1 100.00
aes_csr_rw 1.000s 53.595us 1 1 100.00
aes_csr_aliasing 2.000s 158.080us 1 1 100.00
aes_same_csr_outstanding 2.000s 220.398us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 1 1 100.00
aes_reseed 3.000s 83.174us 1 1 100.00
fault_inject 2 3 66.67
aes_fi 4.000s 475.941us 0 1 0.00
aes_control_fi 2.000s 52.410us 1 1 100.00
aes_cipher_fi 4.000s 68.741us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 2.000s 562.198us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 2.000s 562.198us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 2.000s 562.198us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 2.000s 562.198us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 2.000s 156.444us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 5.000s 415.457us 1 1 100.00
aes_tl_intg_err 2.000s 188.331us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 2.000s 188.331us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
aes_alert_reset 2.000s 76.214us 1 1 100.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 562.198us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 562.198us 1 1 100.00
sec_cm_main_config_sparse 4 4 100.00
aes_smoke 4.000s 223.140us 1 1 100.00
aes_stress 2.000s 117.513us 1 1 100.00
aes_alert_reset 2.000s 76.214us 1 1 100.00
aes_core_fi 2.000s 222.477us 1 1 100.00
sec_cm_gcm_config_sparse 3 3 100.00
aes_config_error 5.000s 225.757us 1 1 100.00
aes_stress 2.000s 117.513us 1 1 100.00
aes_core_fi 2.000s 222.477us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 562.198us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 2.000s 68.980us 1 1 100.00
aes_stress 2.000s 117.513us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 2.000s 117.513us 1 1 100.00
aes_sideload 4.000s 259.382us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 2.000s 68.980us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 2.000s 68.980us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 2.000s 68.980us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 2.000s 68.980us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 2.000s 68.980us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 2.000s 117.513us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 2.000s 117.513us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 4.000s 475.941us 0 1 0.00
sec_cm_main_fsm_redun 3 4 75.00
aes_fi 4.000s 475.941us 0 1 0.00
aes_control_fi 2.000s 52.410us 1 1 100.00
aes_cipher_fi 4.000s 68.741us 1 1 100.00
aes_ctr_fi 2.000s 59.111us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 4.000s 475.941us 0 1 0.00
sec_cm_cipher_fsm_redun 2 3 66.67
aes_fi 4.000s 475.941us 0 1 0.00
aes_control_fi 2.000s 52.410us 1 1 100.00
aes_cipher_fi 4.000s 68.741us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 4.000s 68.741us 1 1 100.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 4.000s 475.941us 0 1 0.00
sec_cm_ctr_fsm_redun 2 3 66.67
aes_fi 4.000s 475.941us 0 1 0.00
aes_control_fi 2.000s 52.410us 1 1 100.00
aes_ctr_fi 2.000s 59.111us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 4.000s 475.941us 0 1 0.00
sec_cm_ctrl_sparse 3 4 75.00
aes_fi 4.000s 475.941us 0 1 0.00
aes_control_fi 2.000s 52.410us 1 1 100.00
aes_cipher_fi 4.000s 68.741us 1 1 100.00
aes_ctr_fi 2.000s 59.111us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
aes_alert_reset 2.000s 76.214us 1 1 100.00
sec_cm_main_fsm_local_esc 3 4 75.00
aes_fi 4.000s 475.941us 0 1 0.00
aes_control_fi 2.000s 52.410us 1 1 100.00
aes_cipher_fi 4.000s 68.741us 1 1 100.00
aes_ctr_fi 2.000s 59.111us 1 1 100.00
sec_cm_cipher_fsm_local_esc 3 4 75.00
aes_fi 4.000s 475.941us 0 1 0.00
aes_control_fi 2.000s 52.410us 1 1 100.00
aes_cipher_fi 4.000s 68.741us 1 1 100.00
aes_ctr_fi 2.000s 59.111us 1 1 100.00
sec_cm_ctr_fsm_local_esc 2 3 66.67
aes_fi 4.000s 475.941us 0 1 0.00
aes_control_fi 2.000s 52.410us 1 1 100.00
aes_ctr_fi 2.000s 59.111us 1 1 100.00
sec_cm_ghash_fsm_local_esc 0 1 0.00
aes_fi 4.000s 475.941us 0 1 0.00
sec_cm_data_reg_local_esc 2 3 66.67
aes_fi 4.000s 475.941us 0 1 0.00
aes_control_fi 2.000s 52.410us 1 1 100.00
aes_cipher_fi 4.000s 68.741us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 4.000s 67.983us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (aes_scoreboard.sv:926) scoreboard [scoreboard] 1 test run
aes_fi 31034941163890102206079839200441006975690441769137501717988382697835289703077 15902
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 4
----| Seen: 3
----| Expected corrupted: 0
UVM_FATAL (cip_base_vseq.sv:1220) [aes_common_vseq] Check failed (vseq_done) 1 test run
aes_stress_all_with_rand_reset 7041747800659565277989208116205194829341770962117718526587404605825503201568 207
UVM_INFO @ 67982934 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---