| V1 |
|
100.00% |
| V2 |
|
100.00% |
| V2S |
|
93.75% |
| V3 |
|
0.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| wake_up | 1 | 1 | 100.00 | |||
| aes_wake_up | 2.000s | 120.404us | 1 | 1 | 100.00 | |
| smoke | 1 | 1 | 100.00 | |||
| aes_smoke | 3.000s | 144.328us | 1 | 1 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| aes_csr_hw_reset | 2.000s | 91.016us | 1 | 1 | 100.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| aes_csr_rw | 2.000s | 85.513us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| aes_csr_bit_bash | 8.000s | 2722.006us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| aes_csr_aliasing | 2.000s | 147.520us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 1 | 1 | 100.00 | |||
| aes_csr_mem_rw_with_rand_reset | 1.000s | 58.708us | 1 | 1 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 2 | 2 | 100.00 | |||
| aes_csr_rw | 2.000s | 85.513us | 1 | 1 | 100.00 | |
| aes_csr_aliasing | 2.000s | 147.520us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| algorithm | 3 | 3 | 100.00 | |||
| aes_smoke | 3.000s | 144.328us | 1 | 1 | 100.00 | |
| aes_config_error | 2.000s | 98.998us | 1 | 1 | 100.00 | |
| aes_stress | 3.000s | 92.624us | 1 | 1 | 100.00 | |
| key_length | 3 | 3 | 100.00 | |||
| aes_smoke | 3.000s | 144.328us | 1 | 1 | 100.00 | |
| aes_config_error | 2.000s | 98.998us | 1 | 1 | 100.00 | |
| aes_stress | 3.000s | 92.624us | 1 | 1 | 100.00 | |
| back2back | 2 | 2 | 100.00 | |||
| aes_stress | 3.000s | 92.624us | 1 | 1 | 100.00 | |
| aes_b2b | 4.000s | 188.802us | 1 | 1 | 100.00 | |
| backpressure | 1 | 1 | 100.00 | |||
| aes_stress | 3.000s | 92.624us | 1 | 1 | 100.00 | |
| multi_message | 4 | 4 | 100.00 | |||
| aes_smoke | 3.000s | 144.328us | 1 | 1 | 100.00 | |
| aes_config_error | 2.000s | 98.998us | 1 | 1 | 100.00 | |
| aes_stress | 3.000s | 92.624us | 1 | 1 | 100.00 | |
| aes_alert_reset | 3.000s | 124.656us | 1 | 1 | 100.00 | |
| failure_test | 3 | 3 | 100.00 | |||
| aes_man_cfg_err | 7.000s | 78.044us | 1 | 1 | 100.00 | |
| aes_config_error | 2.000s | 98.998us | 1 | 1 | 100.00 | |
| aes_alert_reset | 3.000s | 124.656us | 1 | 1 | 100.00 | |
| trigger_clear_test | 1 | 1 | 100.00 | |||
| aes_clear | 3.000s | 103.038us | 1 | 1 | 100.00 | |
| nist_test_vectors | 1 | 1 | 100.00 | |||
| aes_nist_vectors | 3.000s | 212.156us | 1 | 1 | 100.00 | |
| reset_recovery | 1 | 1 | 100.00 | |||
| aes_alert_reset | 3.000s | 124.656us | 1 | 1 | 100.00 | |
| stress | 1 | 1 | 100.00 | |||
| aes_stress | 3.000s | 92.624us | 1 | 1 | 100.00 | |
| sideload | 2 | 2 | 100.00 | |||
| aes_stress | 3.000s | 92.624us | 1 | 1 | 100.00 | |
| aes_sideload | 2.000s | 131.971us | 1 | 1 | 100.00 | |
| deinitialization | 1 | 1 | 100.00 | |||
| aes_deinit | 2.000s | 143.482us | 1 | 1 | 100.00 | |
| stress_all | 1 | 1 | 100.00 | |||
| aes_stress_all | 16.000s | 918.177us | 1 | 1 | 100.00 | |
| alert_test | 1 | 1 | 100.00 | |||
| aes_alert_test | 2.000s | 172.396us | 1 | 1 | 100.00 | |
| tl_d_oob_addr_access | 1 | 1 | 100.00 | |||
| aes_tl_errors | 2.000s | 211.697us | 1 | 1 | 100.00 | |
| tl_d_illegal_access | 1 | 1 | 100.00 | |||
| aes_tl_errors | 2.000s | 211.697us | 1 | 1 | 100.00 | |
| tl_d_outstanding_access | 4 | 4 | 100.00 | |||
| aes_csr_hw_reset | 2.000s | 91.016us | 1 | 1 | 100.00 | |
| aes_csr_rw | 2.000s | 85.513us | 1 | 1 | 100.00 | |
| aes_csr_aliasing | 2.000s | 147.520us | 1 | 1 | 100.00 | |
| aes_same_csr_outstanding | 2.000s | 143.538us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 4 | 4 | 100.00 | |||
| aes_csr_hw_reset | 2.000s | 91.016us | 1 | 1 | 100.00 | |
| aes_csr_rw | 2.000s | 85.513us | 1 | 1 | 100.00 | |
| aes_csr_aliasing | 2.000s | 147.520us | 1 | 1 | 100.00 | |
| aes_same_csr_outstanding | 2.000s | 143.538us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| reseeding | 1 | 1 | 100.00 | |||
| aes_reseed | 2.000s | 144.410us | 1 | 1 | 100.00 | |
| fault_inject | 2 | 3 | 66.67 | |||
| aes_fi | 3.000s | 256.959us | 0 | 1 | 0.00 | |
| aes_control_fi | 2.000s | 92.438us | 1 | 1 | 100.00 | |
| aes_cipher_fi | 2.000s | 67.981us | 1 | 1 | 100.00 | |
| shadow_reg_update_error | 1 | 1 | 100.00 | |||
| aes_shadow_reg_errors | 1.000s | 90.073us | 1 | 1 | 100.00 | |
| shadow_reg_read_clear_staged_value | 1 | 1 | 100.00 | |||
| aes_shadow_reg_errors | 1.000s | 90.073us | 1 | 1 | 100.00 | |
| shadow_reg_storage_error | 1 | 1 | 100.00 | |||
| aes_shadow_reg_errors | 1.000s | 90.073us | 1 | 1 | 100.00 | |
| shadowed_reset_glitch | 1 | 1 | 100.00 | |||
| aes_shadow_reg_errors | 1.000s | 90.073us | 1 | 1 | 100.00 | |
| shadow_reg_update_error_with_csr_rw | 1 | 1 | 100.00 | |||
| aes_shadow_reg_errors_with_csr_rw | 3.000s | 624.776us | 1 | 1 | 100.00 | |
| tl_intg_err | 2 | 2 | 100.00 | |||
| aes_sec_cm | 3.000s | 972.432us | 1 | 1 | 100.00 | |
| aes_tl_intg_err | 2.000s | 115.442us | 1 | 1 | 100.00 | |
| sec_cm_bus_integrity | 1 | 1 | 100.00 | |||
| aes_tl_intg_err | 2.000s | 115.442us | 1 | 1 | 100.00 | |
| sec_cm_lc_escalate_en_intersig_mubi | 1 | 1 | 100.00 | |||
| aes_alert_reset | 3.000s | 124.656us | 1 | 1 | 100.00 | |
| sec_cm_main_config_shadow | 1 | 1 | 100.00 | |||
| aes_shadow_reg_errors | 1.000s | 90.073us | 1 | 1 | 100.00 | |
| sec_cm_gcm_config_shadow | 1 | 1 | 100.00 | |||
| aes_shadow_reg_errors | 1.000s | 90.073us | 1 | 1 | 100.00 | |
| sec_cm_main_config_sparse | 4 | 4 | 100.00 | |||
| aes_smoke | 3.000s | 144.328us | 1 | 1 | 100.00 | |
| aes_stress | 3.000s | 92.624us | 1 | 1 | 100.00 | |
| aes_alert_reset | 3.000s | 124.656us | 1 | 1 | 100.00 | |
| aes_core_fi | 2.000s | 240.975us | 1 | 1 | 100.00 | |
| sec_cm_gcm_config_sparse | 3 | 3 | 100.00 | |||
| aes_config_error | 2.000s | 98.998us | 1 | 1 | 100.00 | |
| aes_stress | 3.000s | 92.624us | 1 | 1 | 100.00 | |
| aes_core_fi | 2.000s | 240.975us | 1 | 1 | 100.00 | |
| sec_cm_aux_config_shadow | 1 | 1 | 100.00 | |||
| aes_shadow_reg_errors | 1.000s | 90.073us | 1 | 1 | 100.00 | |
| sec_cm_aux_config_regwen | 2 | 2 | 100.00 | |||
| aes_readability | 2.000s | 71.297us | 1 | 1 | 100.00 | |
| aes_stress | 3.000s | 92.624us | 1 | 1 | 100.00 | |
| sec_cm_key_sideload | 2 | 2 | 100.00 | |||
| aes_stress | 3.000s | 92.624us | 1 | 1 | 100.00 | |
| aes_sideload | 2.000s | 131.971us | 1 | 1 | 100.00 | |
| sec_cm_key_sw_unreadable | 1 | 1 | 100.00 | |||
| aes_readability | 2.000s | 71.297us | 1 | 1 | 100.00 | |
| sec_cm_data_reg_sw_unreadable | 1 | 1 | 100.00 | |||
| aes_readability | 2.000s | 71.297us | 1 | 1 | 100.00 | |
| sec_cm_key_sec_wipe | 1 | 1 | 100.00 | |||
| aes_readability | 2.000s | 71.297us | 1 | 1 | 100.00 | |
| sec_cm_iv_config_sec_wipe | 1 | 1 | 100.00 | |||
| aes_readability | 2.000s | 71.297us | 1 | 1 | 100.00 | |
| sec_cm_data_reg_sec_wipe | 1 | 1 | 100.00 | |||
| aes_readability | 2.000s | 71.297us | 1 | 1 | 100.00 | |
| sec_cm_data_reg_key_sca | 1 | 1 | 100.00 | |||
| aes_stress | 3.000s | 92.624us | 1 | 1 | 100.00 | |
| sec_cm_key_masking | 1 | 1 | 100.00 | |||
| aes_stress | 3.000s | 92.624us | 1 | 1 | 100.00 | |
| sec_cm_main_fsm_sparse | 0 | 1 | 0.00 | |||
| aes_fi | 3.000s | 256.959us | 0 | 1 | 0.00 | |
| sec_cm_main_fsm_redun | 3 | 4 | 75.00 | |||
| aes_fi | 3.000s | 256.959us | 0 | 1 | 0.00 | |
| aes_control_fi | 2.000s | 92.438us | 1 | 1 | 100.00 | |
| aes_cipher_fi | 2.000s | 67.981us | 1 | 1 | 100.00 | |
| aes_ctr_fi | 1.000s | 55.709us | 1 | 1 | 100.00 | |
| sec_cm_cipher_fsm_sparse | 0 | 1 | 0.00 | |||
| aes_fi | 3.000s | 256.959us | 0 | 1 | 0.00 | |
| sec_cm_cipher_fsm_redun | 2 | 3 | 66.67 | |||
| aes_fi | 3.000s | 256.959us | 0 | 1 | 0.00 | |
| aes_control_fi | 2.000s | 92.438us | 1 | 1 | 100.00 | |
| aes_cipher_fi | 2.000s | 67.981us | 1 | 1 | 100.00 | |
| sec_cm_cipher_ctr_redun | 1 | 1 | 100.00 | |||
| aes_cipher_fi | 2.000s | 67.981us | 1 | 1 | 100.00 | |
| sec_cm_ctr_fsm_sparse | 0 | 1 | 0.00 | |||
| aes_fi | 3.000s | 256.959us | 0 | 1 | 0.00 | |
| sec_cm_ctr_fsm_redun | 2 | 3 | 66.67 | |||
| aes_fi | 3.000s | 256.959us | 0 | 1 | 0.00 | |
| aes_control_fi | 2.000s | 92.438us | 1 | 1 | 100.00 | |
| aes_ctr_fi | 1.000s | 55.709us | 1 | 1 | 100.00 | |
| sec_cm_ghash_fsm_sparse | 0 | 1 | 0.00 | |||
| aes_fi | 3.000s | 256.959us | 0 | 1 | 0.00 | |
| sec_cm_ctrl_sparse | 3 | 4 | 75.00 | |||
| aes_fi | 3.000s | 256.959us | 0 | 1 | 0.00 | |
| aes_control_fi | 2.000s | 92.438us | 1 | 1 | 100.00 | |
| aes_cipher_fi | 2.000s | 67.981us | 1 | 1 | 100.00 | |
| aes_ctr_fi | 1.000s | 55.709us | 1 | 1 | 100.00 | |
| sec_cm_main_fsm_global_esc | 1 | 1 | 100.00 | |||
| aes_alert_reset | 3.000s | 124.656us | 1 | 1 | 100.00 | |
| sec_cm_main_fsm_local_esc | 3 | 4 | 75.00 | |||
| aes_fi | 3.000s | 256.959us | 0 | 1 | 0.00 | |
| aes_control_fi | 2.000s | 92.438us | 1 | 1 | 100.00 | |
| aes_cipher_fi | 2.000s | 67.981us | 1 | 1 | 100.00 | |
| aes_ctr_fi | 1.000s | 55.709us | 1 | 1 | 100.00 | |
| sec_cm_cipher_fsm_local_esc | 3 | 4 | 75.00 | |||
| aes_fi | 3.000s | 256.959us | 0 | 1 | 0.00 | |
| aes_control_fi | 2.000s | 92.438us | 1 | 1 | 100.00 | |
| aes_cipher_fi | 2.000s | 67.981us | 1 | 1 | 100.00 | |
| aes_ctr_fi | 1.000s | 55.709us | 1 | 1 | 100.00 | |
| sec_cm_ctr_fsm_local_esc | 2 | 3 | 66.67 | |||
| aes_fi | 3.000s | 256.959us | 0 | 1 | 0.00 | |
| aes_control_fi | 2.000s | 92.438us | 1 | 1 | 100.00 | |
| aes_ctr_fi | 1.000s | 55.709us | 1 | 1 | 100.00 | |
| sec_cm_ghash_fsm_local_esc | 0 | 1 | 0.00 | |||
| aes_fi | 3.000s | 256.959us | 0 | 1 | 0.00 | |
| sec_cm_data_reg_local_esc | 2 | 3 | 66.67 | |||
| aes_fi | 3.000s | 256.959us | 0 | 1 | 0.00 | |
| aes_control_fi | 2.000s | 92.438us | 1 | 1 | 100.00 | |
| aes_cipher_fi | 2.000s | 67.981us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| stress_all_with_rand_reset | 0 | 1 | 0.00 | |||
| aes_stress_all_with_rand_reset | 24.000s | 1735.472us | 0 | 1 | 0.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_FATAL (aes_scoreboard.sv:926) scoreboard [scoreboard] | 1 test run | |||
| aes_fi | 17324149331260846277691771350409410559104348319382178011458627510141341988390 | 8021 |
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 5
----| Seen: 4
----| Expected corrupted: 0
|
|
| UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues | 1 test run | |||
| aes_stress_all_with_rand_reset | 109840900999073772061097819496839640411659048665070488335901844463296637087105 | 937 |
UVM_INFO @ 1735471977 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|