Simulation Results: alert_handler

 
12/08/2026 15:30:28 DVSim: v1.50.1 sha: 71b9f97 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 86.19 %
  • code
  • 88.94 %
  • assert
  • 98.09 %
  • func
  • 71.55 %
  • line
  • 99.64 %
  • branch
  • 97.83 %
  • cond
  • 90.77 %
  • toggle
  • 83.86 %
  • FSM
  • 72.58 %
Validation stages
V1
100.00%
V2
84.21%
V2S
87.50%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
alert_handler_smoke 33.490s 3688.909us 1 1 100.00
csr_hw_reset 1 1 100.00
alert_handler_csr_hw_reset 6.010s 225.823us 1 1 100.00
csr_rw 1 1 100.00
alert_handler_csr_rw 6.190s 250.567us 1 1 100.00
csr_bit_bash 1 1 100.00
alert_handler_csr_bit_bash 85.120s 1279.771us 1 1 100.00
csr_aliasing 1 1 100.00
alert_handler_csr_aliasing 81.540s 3903.515us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
alert_handler_csr_mem_rw_with_rand_reset 7.590s 1702.629us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
alert_handler_csr_rw 6.190s 250.567us 1 1 100.00
alert_handler_csr_aliasing 81.540s 3903.515us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
esc_accum 1 1 100.00
alert_handler_esc_alert_accum 46.830s 1802.106us 1 1 100.00
esc_timeout 1 1 100.00
alert_handler_esc_intr_timeout 11.690s 187.131us 1 1 100.00
entropy 1 1 100.00
alert_handler_entropy 1267.160s 227190.954us 1 1 100.00
sig_int_fail 1 1 100.00
alert_handler_sig_int_fail 18.930s 1152.234us 1 1 100.00
clk_skew 1 1 100.00
alert_handler_smoke 33.490s 3688.909us 1 1 100.00
random_alerts 1 1 100.00
alert_handler_random_alerts 20.900s 3625.027us 1 1 100.00
random_classes 1 1 100.00
alert_handler_random_classes 16.160s 2872.688us 1 1 100.00
ping_timeout 0 1 0.00
alert_handler_ping_timeout 77.950s 5581.472us 0 1 0.00
lpg 1 2 50.00
alert_handler_lpg 352.010s 27261.887us 0 1 0.00
alert_handler_lpg_stub_clk 2264.630s 57834.320us 1 1 100.00
stress_all 1 1 100.00
alert_handler_stress_all 96.000s 2061.382us 1 1 100.00
alert_handler_entropy_stress_test 0 1 0.00
alert_handler_entropy_stress 6.880s 800.502us 0 1 0.00
alert_handler_alert_accum_saturation 1 1 100.00
alert_handler_alert_accum_saturation 3.380s 211.580us 1 1 100.00
intr_test 1 1 100.00
alert_handler_intr_test 1.580s 8.200us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
alert_handler_tl_errors 6.190s 293.390us 1 1 100.00
tl_d_illegal_access 1 1 100.00
alert_handler_tl_errors 6.190s 293.390us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
alert_handler_csr_hw_reset 6.010s 225.823us 1 1 100.00
alert_handler_csr_rw 6.190s 250.567us 1 1 100.00
alert_handler_csr_aliasing 81.540s 3903.515us 1 1 100.00
alert_handler_same_csr_outstanding 7.480s 176.276us 1 1 100.00
tl_d_partial_access 4 4 100.00
alert_handler_csr_hw_reset 6.010s 225.823us 1 1 100.00
alert_handler_csr_rw 6.190s 250.567us 1 1 100.00
alert_handler_csr_aliasing 81.540s 3903.515us 1 1 100.00
alert_handler_same_csr_outstanding 7.480s 176.276us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
alert_handler_shadow_reg_errors 110.500s 3025.836us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
alert_handler_shadow_reg_errors 110.500s 3025.836us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
alert_handler_shadow_reg_errors 110.500s 3025.836us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
alert_handler_shadow_reg_errors 110.500s 3025.836us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
alert_handler_shadow_reg_errors_with_csr_rw 183.130s 2252.331us 1 1 100.00
tl_intg_err 2 2 100.00
alert_handler_sec_cm 9.600s 436.442us 1 1 100.00
alert_handler_tl_intg_err 55.570s 1389.084us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
alert_handler_tl_intg_err 55.570s 1389.084us 1 1 100.00
sec_cm_config_shadow 1 1 100.00
alert_handler_shadow_reg_errors 110.500s 3025.836us 1 1 100.00
sec_cm_ping_timer_config_regwen 1 1 100.00
alert_handler_smoke 33.490s 3688.909us 1 1 100.00
sec_cm_alert_config_regwen 1 1 100.00
alert_handler_smoke 33.490s 3688.909us 1 1 100.00
sec_cm_alert_loc_config_regwen 1 1 100.00
alert_handler_smoke 33.490s 3688.909us 1 1 100.00
sec_cm_class_config_regwen 1 1 100.00
alert_handler_smoke 33.490s 3688.909us 1 1 100.00
sec_cm_alert_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 18.930s 1152.234us 1 1 100.00
sec_cm_lpg_intersig_mubi 0 1 0.00
alert_handler_lpg 352.010s 27261.887us 0 1 0.00
sec_cm_esc_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 18.930s 1152.234us 1 1 100.00
sec_cm_alert_rx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 1267.160s 227190.954us 1 1 100.00
sec_cm_esc_tx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 1267.160s 227190.954us 1 1 100.00
sec_cm_esc_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 9.600s 436.442us 1 1 100.00
sec_cm_ping_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 9.600s 436.442us 1 1 100.00
sec_cm_esc_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 9.600s 436.442us 1 1 100.00
sec_cm_ping_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 9.600s 436.442us 1 1 100.00
sec_cm_esc_timer_fsm_global_esc 1 1 100.00
alert_handler_sec_cm 9.600s 436.442us 1 1 100.00
sec_cm_accu_ctr_redun 1 1 100.00
alert_handler_sec_cm 9.600s 436.442us 1 1 100.00
sec_cm_esc_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 9.600s 436.442us 1 1 100.00
sec_cm_ping_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 9.600s 436.442us 1 1 100.00
sec_cm_ping_timer_lfsr_redun 1 1 100.00
alert_handler_sec_cm 9.600s 436.442us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
alert_handler_stress_all_with_rand_reset 122.080s 2870.809us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (alert_handler_scoreboard.sv:486) [scoreboard] Check failed intr_state_val == item.d_data (* [*] vs * [*]) reg name: intr_state 1 test run
alert_handler_ping_timeout 56027776867565610178898565057818945692095686341406543225473556235548559346094 105
UVM_INFO @ 5581471703 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (alert_handler_scoreboard.sv:490) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: alert_handler_reg_block.classa_accum_cnt 1 test run
alert_handler_lpg 102203429579120790072766052189530334075397473284123201877729926758483275143585 86
UVM_INFO @ 27261887051 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR sequencer [alert_sender_ping_rsp_seq] Response queue overflow, response was dropped 1 test run
alert_handler_entropy_stress 37141877727166291707949570518184807646268608816606899122097796478067516073297 186
UVM_INFO @ 800502465 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1286) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
alert_handler_stress_all_with_rand_reset 39678213804879229162833936818499534180439987321744670806508491434059568762982 159
UVM_INFO @ 2870809027 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---