Simulation Results: chip

 
12/08/2026 15:30:28 DVSim: v1.50.1 sha: 71b9f97 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 78.23 %
  • code
  • 81.51 %
  • assert
  • 97.50 %
  • func
  • 55.69 %
  • line
  • 94.32 %
  • branch
  • 93.62 %
  • cond
  • 88.94 %
  • toggle
  • 73.52 %
  • FSM
  • 57.14 %
Validation stages
V1
94.44%
V2
87.73%
V2S
100.00%
V3
57.69%
unmapped
63.64%
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_example_tests 4 4 100.00
chip_sw_example_flash 186.220s 3151.492us 1 1 100.00
chip_sw_example_rom 97.490s 2506.083us 1 1 100.00
chip_sw_example_manufacturer 218.920s 3619.101us 1 1 100.00
chip_sw_example_concurrency 225.680s 3569.594us 1 1 100.00
csr_hw_reset 1 1 100.00
chip_csr_hw_reset 338.850s 7769.237us 1 1 100.00
csr_rw 1 1 100.00
chip_csr_rw 367.270s 5092.142us 1 1 100.00
csr_bit_bash 1 1 100.00
chip_csr_bit_bash 408.300s 5602.064us 1 1 100.00
csr_aliasing 1 1 100.00
chip_csr_aliasing 3802.480s 29219.428us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
chip_csr_mem_rw_with_rand_reset 83.540s 3126.258us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
chip_csr_aliasing 3802.480s 29219.428us 1 1 100.00
chip_csr_rw 367.270s 5092.142us 1 1 100.00
xbar_smoke 1 1 100.00
xbar_smoke 7.190s 197.163us 1 1 100.00
chip_sw_gpio_out 1 1 100.00
chip_sw_gpio 316.550s 4026.775us 1 1 100.00
chip_sw_gpio_in 1 1 100.00
chip_sw_gpio 316.550s 4026.775us 1 1 100.00
chip_sw_gpio_irq 1 1 100.00
chip_sw_gpio 316.550s 4026.775us 1 1 100.00
chip_sw_uart_tx_rx 1 1 100.00
chip_sw_uart_tx_rx 389.850s 5453.806us 1 1 100.00
chip_sw_uart_rx_overflow 4 4 100.00
chip_sw_uart_tx_rx 389.850s 5453.806us 1 1 100.00
chip_sw_uart_tx_rx_idx1 467.880s 5180.069us 1 1 100.00
chip_sw_uart_tx_rx_idx2 384.130s 5242.526us 1 1 100.00
chip_sw_uart_tx_rx_idx3 445.830s 5375.730us 1 1 100.00
chip_sw_uart_baud_rate 1 1 100.00
chip_sw_uart_rand_baudrate 384.270s 4227.667us 1 1 100.00
chip_sw_uart_tx_rx_alt_clk_freq 2 2 100.00
chip_sw_uart_tx_rx_alt_clk_freq 409.160s 4712.243us 1 1 100.00
chip_sw_uart_tx_rx_alt_clk_freq_low_speed 392.230s 5251.409us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_pin_mux 1 1 100.00
chip_padctrl_attributes 255.980s 4793.104us 1 1 100.00
chip_padctrl_attributes 1 1 100.00
chip_padctrl_attributes 255.980s 4793.104us 1 1 100.00
chip_sw_sleep_pin_mio_dio_val 1 1 100.00
chip_sw_sleep_pin_mio_dio_val 215.070s 3265.981us 1 1 100.00
chip_sw_sleep_pin_wake 1 1 100.00
chip_sw_sleep_pin_wake 306.470s 8236.807us 1 1 100.00
chip_sw_sleep_pin_retention 1 1 100.00
chip_sw_sleep_pin_retention 222.200s 4040.613us 1 1 100.00
chip_sw_tap_strap_sampling 4 4 100.00
chip_tap_straps_dev 221.130s 4215.441us 1 1 100.00
chip_tap_straps_testunlock0 242.360s 4539.954us 1 1 100.00
chip_tap_straps_rma 271.050s 4901.225us 1 1 100.00
chip_tap_straps_prod 670.990s 10050.291us 1 1 100.00
chip_sw_data_integrity 1 1 100.00
chip_sw_data_integrity_escalation 573.670s 6836.024us 1 1 100.00
chip_sw_instruction_integrity 1 1 100.00
chip_sw_data_integrity_escalation 573.670s 6836.024us 1 1 100.00
chip_sw_ast_clk_outputs 1 1 100.00
chip_sw_ast_clk_outputs 700.320s 8912.799us 1 1 100.00
chip_sw_ast_clk_rst_inputs 0 1 0.00
chip_sw_ast_clk_rst_inputs 1715.310s 16330.581us 0 1 0.00
chip_sw_ast_sys_clk_jitter 10 10 100.00
chip_sw_flash_ctrl_ops_jitter_en 436.410s 4709.817us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 641.120s 7160.256us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 4165.690s 19240.670us 1 1 100.00
chip_sw_aes_enc_jitter_en 207.140s 3817.312us 1 1 100.00
chip_sw_edn_entropy_reqs_jitter 738.050s 6309.803us 1 1 100.00
chip_sw_hmac_enc_jitter_en 210.140s 3668.929us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 1558.380s 12837.334us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 283.880s 4243.451us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 464.790s 5473.404us 1 1 100.00
chip_sw_clkmgr_jitter 196.740s 4158.933us 1 1 100.00
chip_sw_ast_usb_clk_calib 1 1 100.00
chip_sw_usb_ast_clk_calib 237.400s 3614.424us 1 1 100.00
chip_sw_sensor_ctrl_ast_alerts 2 2 100.00
chip_sw_sensor_ctrl_alert 598.430s 8560.470us 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 297.630s 6163.106us 1 1 100.00
chip_sw_sensor_ctrl_ast_status 1 1 100.00
chip_sw_sensor_ctrl_status 206.730s 4186.544us 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 297.630s 6163.106us 1 1 100.00
chip_sw_smoketest 17 17 100.00
chip_sw_flash_scrambling_smoketest 257.610s 4340.251us 1 1 100.00
chip_sw_aes_smoketest 207.280s 3350.790us 1 1 100.00
chip_sw_aon_timer_smoketest 275.080s 4187.438us 1 1 100.00
chip_sw_clkmgr_smoketest 198.920s 3285.173us 1 1 100.00
chip_sw_csrng_smoketest 219.950s 3460.522us 1 1 100.00
chip_sw_entropy_src_smoketest 1242.750s 8886.215us 1 1 100.00
chip_sw_gpio_smoketest 237.860s 3170.962us 1 1 100.00
chip_sw_hmac_smoketest 215.500s 4085.517us 1 1 100.00
chip_sw_kmac_smoketest 218.230s 3997.423us 1 1 100.00
chip_sw_otbn_smoketest 939.440s 6924.712us 1 1 100.00
chip_sw_pwrmgr_smoketest 429.770s 7522.307us 1 1 100.00
chip_sw_pwrmgr_usbdev_smoketest 315.970s 5852.647us 1 1 100.00
chip_sw_rv_plic_smoketest 184.250s 3688.583us 1 1 100.00
chip_sw_rv_timer_smoketest 168.860s 3471.943us 1 1 100.00
chip_sw_rstmgr_smoketest 168.120s 2669.375us 1 1 100.00
chip_sw_sram_ctrl_smoketest 219.930s 3838.769us 1 1 100.00
chip_sw_uart_smoketest 231.510s 3504.304us 1 1 100.00
chip_sw_otp_smoketest 1 1 100.00
chip_sw_otp_ctrl_smoketest 207.730s 3587.466us 1 1 100.00
chip_sw_rom_functests 0 1 0.00
rom_keymgr_functest 440.970s 6182.919us 0 1 0.00
chip_sw_boot 1 1 100.00
chip_sw_uart_tx_rx_bootstrap 9171.420s 60188.196us 1 1 100.00
chip_sw_secure_boot 1 1 100.00
rom_e2e_smoke 3461.450s 16984.944us 1 1 100.00
chip_sw_rom_raw_unlock 0 1 0.00
rom_raw_unlock 682.560s 18024.984us 0 1 0.00
chip_sw_power_idle_load 0 1 0.00
chip_sw_power_idle_load 1320.420s 14981.838us 0 1 0.00
chip_sw_power_sleep_load 0 1 0.00
chip_sw_power_sleep_load 656.580s 15895.720us 0 1 0.00
chip_sw_exit_test_unlocked_bootstrap 1 1 100.00
chip_sw_exit_test_unlocked_bootstrap 7767.910s 53160.204us 1 1 100.00
chip_sw_inject_scramble_seed 1 1 100.00
chip_sw_inject_scramble_seed 9447.630s 58971.363us 1 1 100.00
tl_d_oob_addr_access 0 1 0.00
chip_tl_errors 72.480s 3125.295us 0 1 0.00
tl_d_illegal_access 0 1 0.00
chip_tl_errors 72.480s 3125.295us 0 1 0.00
tl_d_outstanding_access 4 4 100.00
chip_csr_aliasing 3802.480s 29219.428us 1 1 100.00
chip_same_csr_outstanding 1538.480s 15187.136us 1 1 100.00
chip_csr_hw_reset 338.850s 7769.237us 1 1 100.00
chip_csr_rw 367.270s 5092.142us 1 1 100.00
tl_d_partial_access 4 4 100.00
chip_csr_aliasing 3802.480s 29219.428us 1 1 100.00
chip_same_csr_outstanding 1538.480s 15187.136us 1 1 100.00
chip_csr_hw_reset 338.850s 7769.237us 1 1 100.00
chip_csr_rw 367.270s 5092.142us 1 1 100.00
xbar_base_random_sequence 1 1 100.00
xbar_random 33.240s 520.939us 1 1 100.00
xbar_random_delay 6 6 100.00
xbar_smoke_zero_delays 5.760s 42.302us 1 1 100.00
xbar_smoke_large_delays 57.940s 9234.563us 1 1 100.00
xbar_smoke_slow_rsp 38.720s 3794.139us 1 1 100.00
xbar_random_zero_delays 11.890s 119.547us 1 1 100.00
xbar_random_large_delays 31.890s 4938.464us 1 1 100.00
xbar_random_slow_rsp 41.100s 3448.542us 1 1 100.00
xbar_unmapped_address 2 2 100.00
xbar_unmapped_addr 18.320s 216.100us 1 1 100.00
xbar_error_and_unmapped_addr 16.550s 462.017us 1 1 100.00
xbar_error_cases 2 2 100.00
xbar_error_random 15.290s 245.078us 1 1 100.00
xbar_error_and_unmapped_addr 16.550s 462.017us 1 1 100.00
xbar_all_access_same_device 2 2 100.00
xbar_access_same_device 12.790s 110.985us 1 1 100.00
xbar_access_same_device_slow_rsp 25.950s 2545.081us 1 1 100.00
xbar_all_hosts_use_same_source_id 1 1 100.00
xbar_same_source 44.400s 1979.892us 1 1 100.00
xbar_stress_all 2 2 100.00
xbar_stress_all 313.550s 11676.685us 1 1 100.00
xbar_stress_all_with_error 319.850s 11621.514us 1 1 100.00
xbar_stress_with_reset 2 2 100.00
xbar_stress_all_with_rand_reset 338.640s 3296.368us 1 1 100.00
xbar_stress_all_with_reset_error 34.600s 217.644us 1 1 100.00
rom_e2e_smoke 1 1 100.00
rom_e2e_smoke 3461.450s 16984.944us 1 1 100.00
rom_e2e_shutdown_output 1 1 100.00
rom_e2e_shutdown_output 2887.030s 33953.256us 1 1 100.00
rom_e2e_shutdown_exception_c 1 1 100.00
rom_e2e_shutdown_exception_c 3183.780s 15635.232us 1 1 100.00
rom_e2e_boot_policy_valid 15 15 100.00
rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 2562.850s 11310.107us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_dev 3616.560s 16148.911us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_prod 3558.790s 15649.322us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_prod_end 3427.830s 17777.292us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_rma 3199.180s 15258.180us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 2570.570s 12073.160us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_bad_dev 3646.760s 15696.798us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_bad_prod 3313.260s 18504.058us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_bad_prod_end 3449.270s 16216.730us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_bad_rma 3268.330s 15469.701us 1 1 100.00
rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 4927.280s 19634.966us 1 1 100.00
rom_e2e_boot_policy_valid_a_bad_b_good_dev 5814.220s 23947.074us 1 1 100.00
rom_e2e_boot_policy_valid_a_bad_b_good_prod 5976.670s 24450.515us 1 1 100.00
rom_e2e_boot_policy_valid_a_bad_b_good_prod_end 6069.630s 23860.274us 1 1 100.00
rom_e2e_boot_policy_valid_a_bad_b_good_rma 5836.950s 24792.865us 1 1 100.00
rom_e2e_sigverify_always 15 15 100.00
rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 4604.450s 18137.964us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_bad_dev 5830.910s 23355.550us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_bad_prod 6041.670s 23698.709us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_bad_prod_end 5775.450s 24172.919us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_bad_rma 5698.070s 22824.385us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 2310.700s 11599.433us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_nothing_dev 3438.070s 15996.145us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_nothing_prod 3324.010s 14269.723us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_nothing_prod_end 3244.360s 15763.714us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_nothing_rma 3022.870s 13948.964us 1 1 100.00
rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 2657.600s 16782.870us 1 1 100.00
rom_e2e_sigverify_always_a_nothing_b_bad_dev 3214.060s 15766.896us 1 1 100.00
rom_e2e_sigverify_always_a_nothing_b_bad_prod 3239.020s 17207.429us 1 1 100.00
rom_e2e_sigverify_always_a_nothing_b_bad_prod_end 3464.450s 15651.275us 1 1 100.00
rom_e2e_sigverify_always_a_nothing_b_bad_rma 3076.720s 14105.210us 1 1 100.00
rom_e2e_asm_init 5 5 100.00
rom_e2e_asm_init_test_unlocked0 2600.970s 11476.333us 1 1 100.00
rom_e2e_asm_init_dev 3380.100s 16976.119us 1 1 100.00
rom_e2e_asm_init_prod 3824.710s 18858.392us 1 1 100.00
rom_e2e_asm_init_prod_end 3245.070s 15900.634us 1 1 100.00
rom_e2e_asm_init_rma 3304.320s 15182.938us 1 1 100.00
rom_e2e_keymgr_init 1 3 33.33
rom_e2e_keymgr_init_rom_ext_meas 3447.190s 17184.757us 0 1 0.00
rom_e2e_keymgr_init_rom_ext_no_meas 3470.130s 17590.532us 0 1 0.00
rom_e2e_keymgr_init_rom_ext_invalid_meas 6500.480s 29418.743us 1 1 100.00
rom_e2e_static_critical 1 1 100.00
rom_e2e_static_critical 3864.420s 23263.416us 1 1 100.00
chip_sw_adc_ctrl_debug_cable_irq 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 3600.171s 0.000us 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 3600.171s 0.000us 0 1 0.00
chip_sw_aes_enc 2 2 100.00
chip_sw_aes_enc 220.820s 3583.531us 1 1 100.00
chip_sw_aes_enc_jitter_en 207.140s 3817.312us 1 1 100.00
chip_sw_aes_entropy 1 1 100.00
chip_sw_aes_entropy 173.430s 3574.938us 1 1 100.00
chip_sw_aes_idle 1 1 100.00
chip_sw_aes_idle 203.170s 3936.539us 1 1 100.00
chip_sw_aes_sideload 1 1 100.00
chip_sw_keymgr_sideload_aes 1570.520s 11980.936us 1 1 100.00
chip_sw_alert_handler_alerts 0 1 0.00
chip_sw_alert_test 204.000s 3247.110us 0 1 0.00
chip_sw_alert_handler_escalations 1 1 100.00
chip_sw_alert_handler_escalation 421.920s 6454.449us 1 1 100.00
chip_sw_all_escalation_resets 0 1 0.00
chip_sw_all_escalation_resets 263.890s 3722.169us 0 1 0.00
chip_sw_alert_handler_irqs 3 3 100.00
chip_plic_all_irqs_0 571.790s 5467.216us 1 1 100.00
chip_plic_all_irqs_10 257.110s 3716.087us 1 1 100.00
chip_plic_all_irqs_20 437.780s 5003.094us 1 1 100.00
chip_sw_alert_handler_entropy 1 1 100.00
chip_sw_alert_handler_entropy 246.230s 3981.080us 1 1 100.00
chip_sw_alert_handler_crashdump 1 1 100.00
chip_sw_rstmgr_alert_info 1106.670s 14203.907us 1 1 100.00
chip_sw_alert_handler_ping_timeout 1 1 100.00
chip_sw_alert_handler_ping_timeout 301.330s 4854.369us 1 1 100.00
chip_sw_alert_handler_lpg_sleep_mode_alerts 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_alerts 150.430s 2716.924us 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_pings 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_pings 14400.144s 0.000us 0 1 0.00
chip_sw_alert_handler_lpg_clock_off 1 1 100.00
chip_sw_alert_handler_lpg_clkoff 848.130s 8003.252us 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 1197.940s 8694.701us 1 1 100.00
chip_sw_alert_handler_ping_ok 1 1 100.00
chip_sw_alert_handler_ping_ok 940.490s 9259.623us 1 1 100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep 1 1 100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep 10739.900s 254936.130us 1 1 100.00
chip_sw_aon_timer_wakeup_irq 1 1 100.00
chip_sw_aon_timer_irq 253.650s 4446.640us 1 1 100.00
chip_sw_aon_timer_sleep_wakeup 1 1 100.00
chip_sw_pwrmgr_smoketest 429.770s 7522.307us 1 1 100.00
chip_sw_aon_timer_wdog_bark_irq 1 1 100.00
chip_sw_aon_timer_irq 253.650s 4446.640us 1 1 100.00
chip_sw_aon_timer_wdog_bite_reset 0 1 0.00
chip_sw_aon_timer_wdog_bite_reset 468.800s 9457.572us 0 1 0.00
chip_sw_aon_timer_sleep_wdog_bite_reset 0 1 0.00
chip_sw_aon_timer_wdog_bite_reset 468.800s 9457.572us 0 1 0.00
chip_sw_aon_timer_sleep_wdog_sleep_pause 1 1 100.00
chip_sw_aon_timer_sleep_wdog_sleep_pause 435.510s 7909.354us 1 1 100.00
chip_sw_aon_timer_wdog_lc_escalate 1 1 100.00
chip_sw_aon_timer_wdog_lc_escalate 555.450s 8000.089us 1 1 100.00
chip_sw_clkmgr_idle_trans 4 4 100.00
chip_sw_otbn_randomness 660.380s 6354.534us 1 1 100.00
chip_sw_aes_idle 203.170s 3936.539us 1 1 100.00
chip_sw_hmac_enc_idle 195.950s 3465.128us 1 1 100.00
chip_sw_kmac_idle 178.190s 3785.244us 1 1 100.00
chip_sw_clkmgr_off_trans 4 4 100.00
chip_sw_clkmgr_off_aes_trans 342.510s 6696.219us 1 1 100.00
chip_sw_clkmgr_off_hmac_trans 267.630s 6082.991us 1 1 100.00
chip_sw_clkmgr_off_kmac_trans 346.610s 5881.261us 1 1 100.00
chip_sw_clkmgr_off_otbn_trans 362.450s 6651.240us 1 1 100.00
chip_sw_clkmgr_off_peri 1 1 100.00
chip_sw_clkmgr_off_peri 1009.110s 15244.449us 1 1 100.00
chip_sw_clkmgr_div 7 7 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 430.560s 4231.554us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 426.790s 5062.038us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 519.100s 5349.988us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 463.810s 5471.087us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_rma 462.540s 5733.613us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_rma 407.680s 4907.342us 1 1 100.00
chip_sw_ast_clk_outputs 700.320s 8912.799us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 472.380s 7148.044us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw 2 2 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 519.100s 5349.988us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 463.810s 5471.087us 1 1 100.00
chip_sw_clkmgr_jitter 10 10 100.00
chip_sw_flash_ctrl_ops_jitter_en 436.410s 4709.817us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 641.120s 7160.256us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 4165.690s 19240.670us 1 1 100.00
chip_sw_aes_enc_jitter_en 207.140s 3817.312us 1 1 100.00
chip_sw_edn_entropy_reqs_jitter 738.050s 6309.803us 1 1 100.00
chip_sw_hmac_enc_jitter_en 210.140s 3668.929us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 1558.380s 12837.334us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 283.880s 4243.451us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 464.790s 5473.404us 1 1 100.00
chip_sw_clkmgr_jitter 196.740s 4158.933us 1 1 100.00
chip_sw_clkmgr_extended_range 11 11 100.00
chip_sw_clkmgr_jitter_reduced_freq 194.240s 4406.505us 1 1 100.00
chip_sw_flash_ctrl_ops_jitter_en_reduced_freq 401.720s 4803.628us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en_reduced_freq 654.880s 7293.190us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq 4506.300s 25572.612us 1 1 100.00
chip_sw_aes_enc_jitter_en_reduced_freq 226.720s 3983.473us 1 1 100.00
chip_sw_hmac_enc_jitter_en_reduced_freq 230.560s 3625.368us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en_reduced_freq 740.140s 9235.208us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en_reduced_freq 221.550s 3577.922us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq 485.780s 7375.450us 1 1 100.00
chip_sw_flash_init_reduced_freq 1622.500s 31397.174us 1 1 100.00
chip_sw_csrng_edn_concurrency_reduced_freq 10305.860s 89967.310us 1 1 100.00
chip_sw_clkmgr_deep_sleep_frequency 1 1 100.00
chip_sw_ast_clk_outputs 700.320s 8912.799us 1 1 100.00
chip_sw_clkmgr_sleep_frequency 1 1 100.00
chip_sw_clkmgr_sleep_frequency 392.830s 5071.666us 1 1 100.00
chip_sw_clkmgr_reset_frequency 1 1 100.00
chip_sw_clkmgr_reset_frequency 309.500s 3589.283us 1 1 100.00
chip_sw_clkmgr_escalation_reset 0 1 0.00
chip_sw_all_escalation_resets 263.890s 3722.169us 0 1 0.00
chip_sw_clkmgr_alert_handler_clock_enables 1 1 100.00
chip_sw_alert_handler_lpg_clkoff 848.130s 8003.252us 1 1 100.00
chip_sw_csrng_edn_cmd 1 1 100.00
chip_sw_entropy_src_csrng 2326.250s 24432.781us 1 1 100.00
chip_sw_csrng_fuse_en_sw_app_read 0 1 0.00
chip_sw_csrng_fuse_en_sw_app_read_test 185.820s 3403.710us 0 1 0.00
chip_sw_csrng_lc_hw_debug_en 1 1 100.00
chip_sw_csrng_lc_hw_debug_en_test 585.490s 7798.777us 1 1 100.00
chip_sw_csrng_known_answer_tests 1 1 100.00
chip_sw_csrng_kat_test 202.060s 3649.032us 1 1 100.00
chip_sw_edn_entropy_reqs 3 3 100.00
chip_sw_csrng_edn_concurrency 6622.930s 29812.034us 1 1 100.00
chip_sw_entropy_src_ast_rng_req 186.850s 2806.654us 1 1 100.00
chip_sw_edn_entropy_reqs 853.520s 8567.687us 1 1 100.00
chip_sw_entropy_src_ast_rng_req 1 1 100.00
chip_sw_entropy_src_ast_rng_req 186.850s 2806.654us 1 1 100.00
chip_sw_entropy_src_csrng 1 1 100.00
chip_sw_entropy_src_csrng 2326.250s 24432.781us 1 1 100.00
chip_sw_entropy_src_known_answer_tests 1 1 100.00
chip_sw_entropy_src_kat_test 216.940s 3494.219us 1 1 100.00
chip_sw_flash_init 1 1 100.00
chip_sw_flash_init 1607.060s 24519.614us 1 1 100.00
chip_sw_flash_host_access 2 2 100.00
chip_sw_flash_ctrl_access 614.490s 6499.530us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 641.120s 7160.256us 1 1 100.00
chip_sw_flash_ctrl_ops 2 2 100.00
chip_sw_flash_ctrl_ops 412.010s 4077.896us 1 1 100.00
chip_sw_flash_ctrl_ops_jitter_en 436.410s 4709.817us 1 1 100.00
chip_sw_flash_rma_unlocked 1 1 100.00
chip_sw_flash_rma_unlocked 3962.740s 45978.797us 1 1 100.00
chip_sw_flash_scramble 1 1 100.00
chip_sw_flash_init 1607.060s 24519.614us 1 1 100.00
chip_sw_flash_idle_low_power 1 1 100.00
chip_sw_flash_ctrl_idle_low_power 285.890s 4484.237us 1 1 100.00
chip_sw_flash_keymgr_seeds 1 1 100.00
chip_sw_keymgr_key_derivation 2107.310s 15283.254us 1 1 100.00
chip_sw_flash_lc_creator_seed_sw_rw_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 262.520s 4311.168us 0 1 0.00
chip_sw_flash_creator_seed_wipe_on_rma 1 1 100.00
chip_sw_flash_rma_unlocked 3962.740s 45978.797us 1 1 100.00
chip_sw_flash_lc_owner_seed_sw_rw_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 262.520s 4311.168us 0 1 0.00
chip_sw_flash_lc_iso_part_sw_rd_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 262.520s 4311.168us 0 1 0.00
chip_sw_flash_lc_iso_part_sw_wr_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 262.520s 4311.168us 0 1 0.00
chip_sw_flash_lc_seed_hw_rd_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 262.520s 4311.168us 0 1 0.00
chip_sw_flash_lc_escalate_en 0 1 0.00
chip_sw_all_escalation_resets 263.890s 3722.169us 0 1 0.00
chip_sw_flash_prim_tl_access 1 1 100.00
chip_prim_tl_access 287.610s 10975.844us 1 1 100.00
chip_sw_flash_ctrl_clock_freqs 1 1 100.00
chip_sw_flash_ctrl_clock_freqs 609.630s 5698.446us 1 1 100.00
chip_sw_flash_ctrl_escalation_reset 1 1 100.00
chip_sw_flash_crash_alert 503.030s 6781.220us 1 1 100.00
chip_sw_flash_ctrl_write_clear 1 1 100.00
chip_sw_flash_crash_alert 503.030s 6781.220us 1 1 100.00
chip_sw_hmac_enc 2 2 100.00
chip_sw_hmac_enc 230.200s 3596.427us 1 1 100.00
chip_sw_hmac_enc_jitter_en 210.140s 3668.929us 1 1 100.00
chip_sw_hmac_idle 1 1 100.00
chip_sw_hmac_enc_idle 195.950s 3465.128us 1 1 100.00
chip_sw_hmac_all_configurations 0 1 0.00
chip_sw_hmac_oneshot 1760.170s 12018.650us 0 1 0.00
chip_sw_hmac_multistream_mode 0 1 0.00
chip_sw_hmac_multistream 1758.230s 12018.496us 0 1 0.00
chip_sw_i2c_host_tx_rx 3 3 100.00
chip_sw_i2c_host_tx_rx 355.980s 4402.895us 1 1 100.00
chip_sw_i2c_host_tx_rx_idx1 461.190s 6462.128us 1 1 100.00
chip_sw_i2c_host_tx_rx_idx2 477.610s 5500.698us 1 1 100.00
chip_sw_i2c_device_tx_rx 1 1 100.00
chip_sw_i2c_device_tx_rx 318.470s 4332.728us 1 1 100.00
chip_sw_keymgr_key_derivation 2 2 100.00
chip_sw_keymgr_key_derivation 2107.310s 15283.254us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 1558.380s 12837.334us 1 1 100.00
chip_sw_keymgr_sideload_kmac 1 1 100.00
chip_sw_keymgr_sideload_kmac 1029.930s 8410.183us 1 1 100.00
chip_sw_keymgr_sideload_aes 1 1 100.00
chip_sw_keymgr_sideload_aes 1570.520s 11980.936us 1 1 100.00
chip_sw_keymgr_sideload_otbn 0 1 0.00
chip_sw_keymgr_sideload_otbn 4414.690s 20018.690us 0 1 0.00
chip_sw_kmac_enc 3 3 100.00
chip_sw_kmac_mode_cshake 191.170s 3985.296us 1 1 100.00
chip_sw_kmac_mode_kmac 206.270s 3454.709us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 283.880s 4243.451us 1 1 100.00
chip_sw_kmac_app_keymgr 1 1 100.00
chip_sw_keymgr_key_derivation 2107.310s 15283.254us 1 1 100.00
chip_sw_kmac_app_lc 1 1 100.00
chip_sw_lc_ctrl_transition 513.360s 9217.366us 1 1 100.00
chip_sw_kmac_app_rom 1 1 100.00
chip_sw_kmac_app_rom 134.540s 3164.813us 1 1 100.00
chip_sw_kmac_entropy 1 1 100.00
chip_sw_kmac_entropy 1189.420s 8018.345us 1 1 100.00
chip_sw_kmac_idle 1 1 100.00
chip_sw_kmac_idle 178.190s 3785.244us 1 1 100.00
chip_sw_lc_ctrl_alert_handler_escalation 1 1 100.00
chip_sw_alert_handler_escalation 421.920s 6454.449us 1 1 100.00
chip_sw_lc_ctrl_jtag_access 3 3 100.00
chip_tap_straps_dev 221.130s 4215.441us 1 1 100.00
chip_tap_straps_rma 271.050s 4901.225us 1 1 100.00
chip_tap_straps_prod 670.990s 10050.291us 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 159.480s 3149.027us 1 1 100.00
chip_sw_lc_ctrl_init 1 1 100.00
chip_sw_lc_ctrl_transition 513.360s 9217.366us 1 1 100.00
chip_sw_lc_ctrl_transitions 1 1 100.00
chip_sw_lc_ctrl_transition 513.360s 9217.366us 1 1 100.00
chip_sw_lc_ctrl_kmac_req 1 1 100.00
chip_sw_lc_ctrl_transition 513.360s 9217.366us 1 1 100.00
chip_sw_lc_ctrl_key_div 1 1 100.00
chip_sw_keymgr_key_derivation_prod 2084.790s 14467.478us 1 1 100.00
chip_sw_lc_ctrl_broadcast 19 22 86.36
chip_sw_flash_ctrl_lc_rw_en 262.520s 4311.168us 0 1 0.00
chip_sw_flash_rma_unlocked 3962.740s 45978.797us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_test_unlocked0 268.680s 3784.089us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_dev 709.250s 9414.780us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_prod 762.040s 9031.536us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_rma 653.740s 7359.671us 0 1 0.00
chip_sw_lc_ctrl_transition 513.360s 9217.366us 1 1 100.00
chip_sw_keymgr_key_derivation 2107.310s 15283.254us 1 1 100.00
chip_sw_rom_ctrl_integrity_check 427.690s 9751.668us 1 1 100.00
chip_sw_sram_ctrl_execution_main 804.950s 12305.892us 1 1 100.00
chip_prim_tl_access 287.610s 10975.844us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 472.380s 7148.044us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 430.560s 4231.554us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 426.790s 5062.038us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 519.100s 5349.988us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 463.810s 5471.087us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_rma 462.540s 5733.613us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_rma 407.680s 4907.342us 1 1 100.00
chip_tap_straps_dev 221.130s 4215.441us 1 1 100.00
chip_tap_straps_rma 271.050s 4901.225us 1 1 100.00
chip_tap_straps_prod 670.990s 10050.291us 1 1 100.00
chip_rv_dm_lc_disabled 122.250s 2917.830us 0 1 0.00
chip_lc_scrap 4 4 100.00
chip_sw_lc_ctrl_rma_to_scrap 184.040s 3953.690us 1 1 100.00
chip_sw_lc_ctrl_raw_to_scrap 149.410s 4283.199us 1 1 100.00
chip_sw_lc_ctrl_test_locked0_to_scrap 116.850s 4088.550us 1 1 100.00
chip_sw_lc_ctrl_rand_to_scrap 181.220s 3494.314us 1 1 100.00
chip_lc_test_locked 1 2 50.00
chip_sw_lc_walkthrough_testunlocks 2022.140s 31514.835us 1 1 100.00
chip_rv_dm_lc_disabled 122.250s 2917.830us 0 1 0.00
chip_sw_lc_walkthrough 2 5 40.00
chip_sw_lc_walkthrough_dev 947.460s 15190.927us 0 1 0.00
chip_sw_lc_walkthrough_prod 883.310s 11060.921us 0 1 0.00
chip_sw_lc_walkthrough_prodend 877.140s 10116.650us 1 1 100.00
chip_sw_lc_walkthrough_rma 516.870s 7119.237us 0 1 0.00
chip_sw_lc_walkthrough_testunlocks 2022.140s 31514.835us 1 1 100.00
chip_sw_lc_ctrl_volatile_raw_unlock 3 3 100.00
chip_sw_lc_ctrl_volatile_raw_unlock 111.230s 2437.526us 1 1 100.00
chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz 91.280s 3116.450us 1 1 100.00
rom_volatile_raw_unlock 70.100s 2761.304us 1 1 100.00
chip_sw_otbn_op 2 2 100.00
chip_sw_otbn_ecdsa_op_irq 4266.650s 17881.516us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 4165.690s 19240.670us 1 1 100.00
chip_sw_otbn_rnd_entropy 1 1 100.00
chip_sw_otbn_randomness 660.380s 6354.534us 1 1 100.00
chip_sw_otbn_urnd_entropy 1 1 100.00
chip_sw_otbn_randomness 660.380s 6354.534us 1 1 100.00
chip_sw_otbn_idle 1 1 100.00
chip_sw_otbn_randomness 660.380s 6354.534us 1 1 100.00
chip_sw_otbn_mem_scramble 1 1 100.00
chip_sw_otbn_mem_scramble 338.200s 4152.955us 1 1 100.00
chip_otp_ctrl_init 1 1 100.00
chip_sw_lc_ctrl_transition 513.360s 9217.366us 1 1 100.00
chip_sw_otp_ctrl_keys 5 5 100.00
chip_sw_flash_init 1607.060s 24519.614us 1 1 100.00
chip_sw_otbn_mem_scramble 338.200s 4152.955us 1 1 100.00
chip_sw_keymgr_key_derivation 2107.310s 15283.254us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access 386.610s 5024.294us 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 154.830s 2560.377us 1 1 100.00
chip_sw_otp_ctrl_entropy 5 5 100.00
chip_sw_flash_init 1607.060s 24519.614us 1 1 100.00
chip_sw_otbn_mem_scramble 338.200s 4152.955us 1 1 100.00
chip_sw_keymgr_key_derivation 2107.310s 15283.254us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access 386.610s 5024.294us 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 154.830s 2560.377us 1 1 100.00
chip_sw_otp_ctrl_program 1 1 100.00
chip_sw_lc_ctrl_transition 513.360s 9217.366us 1 1 100.00
chip_sw_otp_ctrl_program_error 1 1 100.00
chip_sw_lc_ctrl_program_error 395.390s 6670.795us 1 1 100.00
chip_sw_otp_ctrl_hw_cfg0 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 159.480s 3149.027us 1 1 100.00
chip_sw_otp_ctrl_lc_signals 5 6 83.33
chip_sw_otp_ctrl_lc_signals_test_unlocked0 268.680s 3784.089us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_dev 709.250s 9414.780us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_prod 762.040s 9031.536us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_rma 653.740s 7359.671us 0 1 0.00
chip_sw_lc_ctrl_transition 513.360s 9217.366us 1 1 100.00
chip_prim_tl_access 287.610s 10975.844us 1 1 100.00
chip_sw_otp_prim_tl_access 1 1 100.00
chip_prim_tl_access 287.610s 10975.844us 1 1 100.00
chip_sw_otp_ctrl_dai_lock 1 1 100.00
chip_sw_otp_ctrl_dai_lock 926.970s 8978.336us 1 1 100.00
chip_sw_pwrmgr_external_full_reset 0 1 0.00
chip_sw_pwrmgr_full_aon_reset 120.500s 3149.476us 0 1 0.00
chip_sw_pwrmgr_random_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_wake_ups 1450.950s 31235.172us 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups 291.180s 7661.121us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_por_reset 0 1 0.00
chip_sw_pwrmgr_deep_sleep_por_reset 399.030s 9698.276us 0 1 0.00
chip_sw_pwrmgr_normal_sleep_por_reset 1 1 100.00
chip_sw_pwrmgr_normal_sleep_por_reset 559.130s 9364.045us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups 1472.140s 30949.821us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 0 2 0.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 277.420s 6800.331us 0 1 0.00
chip_sw_aon_timer_wdog_bite_reset 468.800s 9457.572us 0 1 0.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 1172.480s 16386.885us 1 1 100.00
chip_sw_pwrmgr_wdog_reset 1 1 100.00
chip_sw_pwrmgr_wdog_reset 405.120s 5811.603us 1 1 100.00
chip_sw_pwrmgr_power_glitch_reset 0 1 0.00
chip_sw_pwrmgr_full_aon_reset 120.500s 3149.476us 0 1 0.00
chip_sw_pwrmgr_main_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_main_power_glitch_reset 338.350s 6486.235us 1 1 100.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset 0 1 0.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset 1145.690s 15289.853us 0 1 0.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset 408.710s 9982.495us 1 1 100.00
chip_sw_pwrmgr_sleep_power_glitch_reset 0 1 0.00
chip_sw_pwrmgr_sleep_power_glitch_reset 208.260s 3653.760us 0 1 0.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 0 1 0.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 285.840s 6664.079us 0 1 0.00
chip_sw_pwrmgr_sysrst_ctrl_reset 2 2 100.00
chip_sw_pwrmgr_sysrst_ctrl_reset 742.750s 7357.489us 1 1 100.00
chip_sw_pwrmgr_all_reset_reqs 1003.170s 12557.869us 1 1 100.00
chip_sw_pwrmgr_b2b_sleep_reset_req 1 1 100.00
chip_sw_pwrmgr_b2b_sleep_reset_req 2227.390s 27223.646us 1 1 100.00
chip_sw_pwrmgr_sleep_disabled 1 1 100.00
chip_sw_pwrmgr_sleep_disabled 184.040s 3774.956us 1 1 100.00
chip_sw_pwrmgr_escalation_reset 0 1 0.00
chip_sw_all_escalation_resets 263.890s 3722.169us 0 1 0.00
chip_sw_rom_access 1 1 100.00
chip_sw_rom_ctrl_integrity_check 427.690s 9751.668us 1 1 100.00
chip_sw_rom_ctrl_integrity_check 1 1 100.00
chip_sw_rom_ctrl_integrity_check 427.690s 9751.668us 1 1 100.00
chip_sw_rstmgr_non_sys_reset_info 3 4 75.00
chip_sw_pwrmgr_all_reset_reqs 1003.170s 12557.869us 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 285.840s 6664.079us 0 1 0.00
chip_sw_pwrmgr_wdog_reset 405.120s 5811.603us 1 1 100.00
chip_sw_pwrmgr_smoketest 429.770s 7522.307us 1 1 100.00
chip_sw_rstmgr_sys_reset_info 1 1 100.00
chip_rv_dm_ndm_reset_req 484.650s 7008.850us 1 1 100.00
chip_sw_rstmgr_cpu_info 1 1 100.00
chip_sw_rstmgr_cpu_info 545.110s 9403.387us 1 1 100.00
chip_sw_rstmgr_sw_req_reset 1 1 100.00
chip_sw_rstmgr_sw_req 410.560s 6056.724us 1 1 100.00
chip_sw_rstmgr_alert_info 1 1 100.00
chip_sw_rstmgr_alert_info 1106.670s 14203.907us 1 1 100.00
chip_sw_rstmgr_sw_rst 1 1 100.00
chip_sw_rstmgr_sw_rst 267.520s 4257.532us 1 1 100.00
chip_sw_rstmgr_escalation_reset 0 1 0.00
chip_sw_all_escalation_resets 263.890s 3722.169us 0 1 0.00
chip_sw_rstmgr_alert_handler_reset_enables 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 1197.940s 8694.701us 1 1 100.00
chip_sw_nmi_irq 1 1 100.00
chip_sw_rv_core_ibex_nmi_irq 513.260s 5288.341us 1 1 100.00
chip_sw_rv_core_ibex_rnd 1 1 100.00
chip_sw_rv_core_ibex_rnd 557.370s 5536.737us 1 1 100.00
chip_sw_rv_core_ibex_address_translation 1 1 100.00
chip_sw_rv_core_ibex_address_translation 189.600s 2729.981us 1 1 100.00
chip_sw_rv_core_ibex_icache_scrambled_access 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 154.830s 2560.377us 1 1 100.00
chip_sw_rv_core_ibex_fault_dump 1 1 100.00
chip_sw_rstmgr_cpu_info 545.110s 9403.387us 1 1 100.00
chip_sw_rv_core_ibex_double_fault 1 1 100.00
chip_sw_rstmgr_cpu_info 545.110s 9403.387us 1 1 100.00
chip_sw_rv_core_ibex_mcounteren_writable 1 1 100.00
chip_sw_rv_core_ibex_mcounteren_writable 232.280s 2907.361us 1 1 100.00
chip_jtag_csr_rw 1 1 100.00
chip_jtag_csr_rw 1057.440s 15123.519us 1 1 100.00
chip_jtag_mem_access 1 1 100.00
chip_jtag_mem_access 1438.600s 16290.730us 1 1 100.00
chip_rv_dm_ndm_reset_req 1 1 100.00
chip_rv_dm_ndm_reset_req 484.650s 7008.850us 1 1 100.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 0 1 0.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 263.450s 4408.167us 0 1 0.00
chip_rv_dm_access_after_wakeup 0 1 0.00
chip_sw_rv_dm_access_after_wakeup 1441.240s 13616.136us 0 1 0.00
chip_sw_rv_dm_jtag_tap_sel 1 1 100.00
chip_tap_straps_rma 271.050s 4901.225us 1 1 100.00
chip_rv_dm_lc_disabled 0 1 0.00
chip_rv_dm_lc_disabled 122.250s 2917.830us 0 1 0.00
chip_sw_plic_all_irqs 3 3 100.00
chip_plic_all_irqs_0 571.790s 5467.216us 1 1 100.00
chip_plic_all_irqs_10 257.110s 3716.087us 1 1 100.00
chip_plic_all_irqs_20 437.780s 5003.094us 1 1 100.00
chip_sw_plic_sw_irq 1 1 100.00
chip_sw_plic_sw_irq 187.180s 3514.036us 1 1 100.00
chip_sw_timer 1 1 100.00
chip_sw_rv_timer_irq 175.770s 3986.001us 1 1 100.00
chip_sw_spi_device_flash_mode 1 1 100.00
rom_e2e_smoke 3461.450s 16984.944us 1 1 100.00
chip_sw_spi_device_pass_through 1 1 100.00
chip_sw_spi_device_pass_through 301.750s 5260.269us 1 1 100.00
chip_sw_spi_device_pass_through_collision 0 1 0.00
chip_sw_spi_device_pass_through_collision 220.870s 4396.373us 0 1 0.00
chip_sw_spi_device_tpm 1 1 100.00
chip_sw_spi_device_tpm 220.440s 3838.313us 1 1 100.00
chip_sw_spi_host_tx_rx 1 1 100.00
chip_sw_spi_host_tx_rx 195.370s 4073.918us 1 1 100.00
chip_sw_sram_scrambled_access 2 2 100.00
chip_sw_sram_ctrl_scrambled_access 386.610s 5024.294us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 464.790s 5473.404us 1 1 100.00
chip_sw_sleep_sram_ret_contents 2 2 100.00
chip_sw_sleep_sram_ret_contents_no_scramble 458.140s 11227.161us 1 1 100.00
chip_sw_sleep_sram_ret_contents_scramble 650.900s 10772.108us 1 1 100.00
chip_sw_sram_execution 1 1 100.00
chip_sw_sram_ctrl_execution_main 804.950s 12305.892us 1 1 100.00
chip_sw_sram_lc_escalation 1 2 50.00
chip_sw_all_escalation_resets 263.890s 3722.169us 0 1 0.00
chip_sw_data_integrity_escalation 573.670s 6836.024us 1 1 100.00
chip_sw_sysrst_ctrl_reset 1 2 50.00
chip_sw_pwrmgr_sysrst_ctrl_reset 742.750s 7357.489us 1 1 100.00
chip_sw_sysrst_ctrl_reset 1121.960s 24710.342us 0 1 0.00
chip_sw_sysrst_ctrl_inputs 1 1 100.00
chip_sw_sysrst_ctrl_inputs 236.080s 3903.693us 1 1 100.00
chip_sw_sysrst_ctrl_outputs 1 1 100.00
chip_sw_sysrst_ctrl_outputs 281.750s 4012.349us 1 1 100.00
chip_sw_sysrst_ctrl_in_irq 1 1 100.00
chip_sw_sysrst_ctrl_in_irq 373.370s 4770.407us 1 1 100.00
chip_sw_sysrst_ctrl_sleep_wakeup 0 1 0.00
chip_sw_sysrst_ctrl_reset 1121.960s 24710.342us 0 1 0.00
chip_sw_sysrst_ctrl_sleep_reset 0 1 0.00
chip_sw_sysrst_ctrl_reset 1121.960s 24710.342us 0 1 0.00
chip_sw_sysrst_ctrl_ec_rst_l 1 1 100.00
chip_sw_sysrst_ctrl_ec_rst_l 2783.290s 21068.231us 1 1 100.00
chip_sw_sysrst_ctrl_flash_wp_l 1 1 100.00
chip_sw_sysrst_ctrl_ec_rst_l 2783.290s 21068.231us 1 1 100.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup 1 2 50.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup 408.380s 8138.726us 1 1 100.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 3600.171s 0.000us 0 1 0.00
chip_sw_usbdev_vbus 1 1 100.00
chip_sw_usbdev_vbus 171.790s 3677.741us 1 1 100.00
chip_sw_usbdev_pullup 1 1 100.00
chip_sw_usbdev_pullup 231.490s 4037.705us 1 1 100.00
chip_sw_usbdev_aon_pullup 1 1 100.00
chip_sw_usbdev_aon_pullup 300.480s 4296.212us 1 1 100.00
chip_sw_usbdev_setup_rx 1 1 100.00
chip_sw_usbdev_setuprx 313.590s 3928.339us 1 1 100.00
chip_sw_usbdev_config_host 1 1 100.00
chip_sw_usbdev_config_host 1110.650s 8319.194us 1 1 100.00
chip_sw_usbdev_pincfg 1 1 100.00
chip_sw_usbdev_pincfg 5442.420s 32930.186us 1 1 100.00
chip_sw_usbdev_tx_rx 1 1 100.00
chip_sw_usbdev_dpi 2075.910s 12231.831us 1 1 100.00
chip_sw_usbdev_toggle_restore 1 1 100.00
chip_sw_usbdev_toggle_restore 194.430s 3590.617us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_aes_masking_off 1 1 100.00
chip_sw_aes_masking_off 264.300s 3543.545us 1 1 100.00
chip_sw_rv_core_ibex_lockstep_glitch 1 1 100.00
chip_sw_rv_core_ibex_lockstep_glitch 82.700s 2640.928us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_coremark 1 1 100.00
chip_sw_coremark 11969.060s 69377.211us 1 1 100.00
chip_sw_power_max_load 1 1 100.00
chip_sw_power_virus 1174.620s 6965.208us 1 1 100.00
rom_e2e_debug 0 3 0.00
rom_e2e_jtag_debug_test_unlocked0 201.590s 5070.344us 0 1 0.00
rom_e2e_jtag_debug_dev 703.690s 14476.139us 0 1 0.00
rom_e2e_jtag_debug_rma 533.150s 7809.732us 0 1 0.00
rom_e2e_jtag_inject 0 3 0.00
rom_e2e_jtag_inject_test_unlocked0 84.850s 2931.592us 0 1 0.00
rom_e2e_jtag_inject_dev 92.730s 2578.282us 0 1 0.00
rom_e2e_jtag_inject_rma 155.280s 4217.279us 0 1 0.00
rom_e2e_self_hash 0 1 0.00
rom_e2e_self_hash 117.773s 0.000us 0 1 0.00
chip_sw_clkmgr_jitter_cycle_measurements 0 1 0.00
chip_sw_clkmgr_jitter_frequency 368.460s 3564.220us 0 1 0.00
chip_sw_edn_boot_mode 1 1 100.00
chip_sw_edn_boot_mode 415.780s 3363.500us 1 1 100.00
chip_sw_edn_auto_mode 1 1 100.00
chip_sw_edn_auto_mode 795.160s 5194.070us 1 1 100.00
chip_sw_edn_sw_mode 1 1 100.00
chip_sw_edn_sw_mode 1144.240s 7628.789us 1 1 100.00
chip_sw_edn_kat 1 1 100.00
chip_sw_edn_kat 281.810s 3205.146us 1 1 100.00
chip_sw_flash_memory_protection 1 1 100.00
chip_sw_flash_ctrl_mem_protection 708.360s 6446.465us 1 1 100.00
chip_sw_otp_ctrl_vendor_test_csr_access 1 1 100.00
chip_sw_otp_ctrl_vendor_test_csr_access 194.220s 3308.822us 1 1 100.00
chip_sw_otp_ctrl_escalation 0 1 0.00
chip_sw_otp_ctrl_escalation 201.580s 3128.095us 0 1 0.00
chip_sw_sensor_ctrl_deep_sleep_wake_up 1 1 100.00
chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up 352.070s 7890.267us 1 1 100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active 1 1 100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active 462.250s 7328.802us 1 1 100.00
chip_sw_all_resets 1 1 100.00
chip_sw_pwrmgr_all_reset_reqs 1003.170s 12557.869us 1 1 100.00
chip_rv_dm_perform_debug 0 3 0.00
rom_e2e_jtag_debug_test_unlocked0 201.590s 5070.344us 0 1 0.00
rom_e2e_jtag_debug_dev 703.690s 14476.139us 0 1 0.00
rom_e2e_jtag_debug_rma 533.150s 7809.732us 0 1 0.00
chip_sw_rv_dm_access_after_hw_reset 0 1 0.00
chip_sw_rv_dm_access_after_escalation_reset 250.840s 3954.454us 0 1 0.00
chip_sw_plic_alerts 0 1 0.00
chip_sw_all_escalation_resets 263.890s 3722.169us 0 1 0.00
tick_configuration 1 1 100.00
chip_sw_rv_timer_systick_test 5575.340s 39204.448us 1 1 100.00
counter_wrap 1 1 100.00
chip_sw_rv_timer_systick_test 5575.340s 39204.448us 1 1 100.00
chip_sw_spi_device_output_when_disabled_or_sleeping 1 1 100.00
chip_sw_spi_device_pinmux_sleep_retention 229.040s 4016.401us 1 1 100.00
chip_sw_uart_watermarks 1 1 100.00
chip_sw_uart_tx_rx 389.850s 5453.806us 1 1 100.00
chip_sw_usbdev_stream 1 1 100.00
chip_sw_usbdev_stream 3574.610s 19058.610us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 7 11 63.64
chip_sival_flash_info_access 237.000s 3552.034us 1 1 100.00
chip_sw_rstmgr_rst_cnsty_escalation 23.640s 10.360us 0 1 0.00
chip_sw_otp_ctrl_rot_auth_config 10.790s 0.000us 0 1 0.00
chip_sw_otp_ctrl_ecc_error_vendor_test 196.140s 3171.334us 1 1 100.00
chip_sw_otp_ctrl_descrambling 240.690s 3856.583us 1 1 100.00
chip_sw_pwrmgr_lowpower_cancel 292.700s 4286.642us 1 1 100.00
chip_sw_pwrmgr_sleep_wake_5_bug 8.513s 0.000us 0 1 0.00
chip_sw_flash_ctrl_write_clear 208.130s 3825.473us 1 1 100.00
ate_bootstrap_flash_erase 610.070s 10010.360us 0 1 0.00
ate_bootstrap_one_frame 6570.000s 43608.065us 1 1 100.00
ate_bootstrap_disjoint 10060.210s 79280.169us 1 1 100.00

Error Messages

   Test seed line log context
Error-[NOA] Null object access 6 test runs
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 25047872926345606156524560043212134918500004724434436236830264364346300932434 342
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_test_unlocked0 71723598696306288870381819126812510922113520469871196031102677089608179978908 334
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_rma 112942529358455032433207141646275410358620122109122648902174449763195610767510 367
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 903
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_test_unlocked0 113121600482427516278693563963247713555202649111401215134841066438385847069712 318
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_dev 35174260986579162759312962040014001018773773310850215983652081547096814179616 318
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_rma 45342704509252823721749846837562705300359308413712030649940205474747722238663 322
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
Offending '(rstreqs[*] && (reset_cause == HwReq))' 5 test runs
chip_sw_pwrmgr_random_sleep_all_reset_reqs 13075145159007249763928613690667418378648321192966534641344187083297588223015 324
UVM_ERROR @ 6664.079500 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 6664.079500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 88198478599507316939438624016004376031520028018793079070424764162429452439750 323
UVM_ERROR @ 6800.331000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 6800.331000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_deep_sleep_por_reset 51399807897863146869474288125818089063269504822279145182538230586872443079186 334
UVM_ERROR @ 9698.276000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 9698.276000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_sysrst_ctrl_reset 80898430132383582129656784806638476277492347822609877901637828298871576161271 343
UVM_ERROR @ 24710.342000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 24710.342000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_aon_timer_wdog_bite_reset 49735307768098339877679795977768113601757136126831528058534420319455095259929 328
UVM_ERROR @ 9457.572000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 9457.572000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))' 3 test runs
chip_sw_all_escalation_resets 70385643515784249040300325401957654143195594640508401252211306080629553432379 326
UVM_ERROR @ 3722.169226 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 3722.169226 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_otp_ctrl_escalation 23833205275086369883626425666118178059116924512021167811876842271462917038522 325
UVM_ERROR @ 3128.095112 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 3128.095112 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_csrng_fuse_en_sw_app_read_test 27691355034940366809109538904258925974273409772927703658024568857957587862139 321
UVM_ERROR @ 3403.709850 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 3403.709850 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected 3 test runs
chip_sw_lc_walkthrough_dev 47193813849208276889253691699586586191425731474322883558011704574794699560700 383
UVM_INFO @ 15190.926565 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_prod 27362892251425834024992971818913348157689147631917578600584674435420172417211 383
UVM_INFO @ 11060.921068 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_rma 90071819370002870190073708252670794310595000307200868537494219294203853425244 355
UVM_INFO @ 7119.236676 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:322) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns 3 test runs
chip_sw_hmac_oneshot 6811411026494258692463983553904732410969258792725902772434196641469063597669 345
UVM_INFO @ 12018.649851 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_hmac_multistream 5565051337746579400570902150955237211882254723238626809851487830523168003435 319
UVM_INFO @ 12018.495545 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_keymgr_sideload_otbn 115389636948406173699416284466302396927875476737772556204452838576161150640863 343
UVM_INFO @ 20018.689790 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$fell((pwrmgr_data_o.done == MuBi4True)))' 2 test runs
chip_sw_pwrmgr_sleep_power_glitch_reset 26369493790907609962057102068157854978709022068464243193824442487840797528786 322
UVM_ERROR @ 3653.760475 us: (rom_ctrl.sv:590) [ASSERT FAILED] PwrmgrDataChk_A
UVM_INFO @ 3653.760475 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_random_sleep_power_glitch_reset 100341130780788920952079978731913381911906455330099705262493144820484854301297 361
UVM_ERROR @ 15289.853388 us: (rom_ctrl.sv:590) [ASSERT FAILED] PwrmgrDataChk_A
UVM_INFO @ 15289.853388 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes 2 test runs
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 87094613268355173370828042647275730396537050278649577384900225419554021708408 None
chip_sw_alert_handler_lpg_sleep_mode_pings 105670154541953913766283260500532377432765809517289697839794148365619193304022 None
UVM_ERROR @ * us: (cip_base_scoreboard.sv:618) scoreboard [scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted *, but saw *). 2 test runs
chip_tl_errors 74962131654902212028302471476051286735272134819224319478945477078714588907134 226
TL item was: req: (cip_tl_seq_item@40991) { a_addr: 'h10364 a_data: 'h7e832430 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h3a a_opcode: 'h4 a_user: 'h1b65f d_param: 'h0 d_source: 'h3a d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 3125.295419 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_csr_mem_rw_with_rand_reset 96201530510822090537677277046006955729711301236058852624283348366223909415764 233
TL item was: req: (cip_tl_seq_item@33303) { a_addr: 'h10714 a_data: 'h5e1340c5 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h2d a_opcode: 'h4 a_user: 'h1b183 d_param: 'h0 d_source: 'h2d d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 3126.257900 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$'] 2 test runs
chip_sw_pwrmgr_sleep_wake_5_bug 21987453818020787013982944688698224117288666933519878930226487244266143664731 None
---- STDERR ----
Another command (pid=2280119) is running. Waiting for it to complete on the server (server_pid=266506)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_self_hash 6607195022312337161001899824173020024888946181610937876205339278852160857584 None
Another command (pid=442899) is running. Waiting for it to complete on the server (server_pid=266506)...
Another command (pid=477816) is running. Waiting for it to complete on the server (server_pid=266506)...
Another command (pid=478205) is running. Waiting for it to complete on the server (server_pid=266506)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
UVM_FATAL @ * us: (sec_cm_pkg.sv:48) [sec_cm_pkg::find_sec_cm_if_proxy] no proxy with path *rstmgr.u_d0_spi_host*.leaf_rst_path 1 test run
chip_sw_rstmgr_rst_cnsty_escalation 82014657308305794209235128853955593368028054282600420112740799848277244184097 310
UVM_INFO @ 10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_spi_passthrough_collision_vseq.sv:183) virtual_sequencer [chip_sw_spi_passthrough_collision_vseq] Compare mismatch 1 test run
chip_sw_spi_device_pass_through_collision 78931332902970750010230488186751552290194790567955346722057022180571264392705 338
host_rsp:
-------------------------------------------------------------------------
Name Type Size Value
-------------------------------------------------------------------------
UVM_ERROR @ * us: (sw_logger_if.sv:526) [flash_ctrl_lc_rw_en_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected 1 test run
chip_sw_flash_ctrl_lc_rw_en 82626700661691697725238567961376971307492740984473004991952688887664639730359 318
UVM_INFO @ 4311.168475 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to * 1 test run
chip_sw_otp_ctrl_lc_signals_rma 7085397239079253163856129855435403587565663657283275833966232295739015259534 351
UVM_INFO @ 7359.670704 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[Otp]] file otp_img_test_unlocked0_manuf_empty.*.vmem could not be opened for r mode 1 test run
chip_sw_otp_ctrl_rot_auth_config 7374673437863017349613198682641742083375721665725885557949089013388293067872 297
UVM_INFO @ 0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '((~rst_ni) === (~seed_en_q))' 1 test run
chip_sw_pwrmgr_full_aon_reset 85472384089936551499661663158482554180102879266946676660891307481872976662558 312
UVM_ERROR @ 3149.475775 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A
UVM_INFO @ 3149.475775 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:366)] CHECK-fail: Expect alert *! 1 test run
chip_sw_alert_test 50049246859568325173891806298859545321447593572429270986185123393150361784091 316
UVM_INFO @ 3247.110033 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0) 1 test run
chip_sw_alert_handler_lpg_sleep_mode_alerts 1439568329110092262201962053534976842198327331435549149733795212074338081831 322
UVM_INFO @ 2716.924446 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [clkmgr_jitter_frequency_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected 1 test run
chip_sw_clkmgr_jitter_frequency 78227382259047228670174715208621705888783463279339772759872230366230555018871 352
UVM_INFO @ 3564.219729 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_rv_dm_access_after_wakeup_vseq.sv:93) [chip_sw_rv_dm_access_after_wakeup_vseq] Timed out waiting for device to wakeup from deep sleep. 1 test run
chip_sw_rv_dm_access_after_wakeup 55514891114864714831912977926529309149042171417749326736123127782250496673095 344
UVM_INFO @ 13616.135668 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(rv_jtag_o == '0)' 1 test run
chip_sw_rv_dm_access_after_escalation_reset 33887321305584944299548620255380199359766583878770568391861543708069200808754 326
UVM_ERROR @ 3954.454074 us: (pinmux_strap_sampling.sv:516) [ASSERT FAILED] RvTapOff1_A
UVM_INFO @ 3954.454074 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_vseq.sv:660) [chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch 1 test run
chip_rv_dm_lc_disabled 34561242179272782836163161632653516388250983175459455857363996081634093583782 230
UVM_INFO @ 2917.830097 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_power_idle_load_vseq.sv:24) [chip_sw_power_idle_load_vseq] timeout waiting for SW sync GPIO (*) 1 test run
chip_sw_power_idle_load 7744108178402913587297828237246445023654089718186647782953384395949208466329 327
UVM_INFO @ 14981.838113 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_power_sleep_load_vseq.sv:47) [chip_sw_power_sleep_load_vseq] timeout waiting for SW sync GPIO (*) 1 test run
chip_sw_power_sleep_load 36684400429150770093805591245101755308038797445478161521396136236230940419083 346
UVM_INFO @ 15895.720436 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/lib/testing/autogen/isr_testutils.c:41)] CHECK-fail: Only adc_ctrl IRQ * expected to fire. Actual IRQ state = * 1 test run
chip_sw_ast_clk_rst_inputs 41299340581548616702322467517144778071374535830128654192214691447240090683388 336
UVM_INFO @ 16330.581370 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (csr_utils_pkg.sv:619) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout chip_reg_block.spi_device.cmd_info_*.opcode (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=1) 1 test run
ate_bootstrap_flash_erase 47459065527232743768893259202672108491426935427823008738799894421344640328419 281
UVM_INFO @ 10010.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred! 1 test run
rom_e2e_jtag_debug_dev 70287113011489147019650871211558201994316347129212181093467211406064380160309 345
UVM_INFO @ 14476.139179 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rom_e2e_keymgr_init_otp_meas_sim_dv(sw/device/silicon_creator/rom/e2e/keymgr/rom_e2e_keymgr_init_test.c:38)] DIF-fail: dif_otp_ctrl_get_digest( &otp_ctrl, kDifOtpCtrlPartitionCreatorSwCfg, &creator_digest) returns * 1 test run
rom_e2e_keymgr_init_rom_ext_meas 54043159807693636620066901747048804536235495523342101241956571494330525481328 328
UVM_INFO @ 17184.756589 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rom_e2e_keymgr_init_otp_no_meas_sim_dv(sw/device/silicon_creator/rom/e2e/keymgr/rom_e2e_keymgr_init_test.c:38)] DIF-fail: dif_otp_ctrl_get_digest( &otp_ctrl, kDifOtpCtrlPartitionCreatorSwCfg, &creator_digest) returns * 1 test run
rom_e2e_keymgr_init_rom_ext_no_meas 97563355755599643791592749227201422023606735153962422644541987328223124802626 328
UVM_INFO @ 17590.532068 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_lc_raw_unlock_vseq.sv:57) [chip_sw_lc_raw_unlock_vseq] Timed out waiting for clkmgr to confirm extclk enablement 1 test run
rom_raw_unlock 76756642594907904947310514224756782954967300223406406140479600123325523545931 337
UVM_INFO @ 18024.983830 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '$stable(key_data_i)' 1 test run
rom_keymgr_functest 17583739270479326262322020193241781114285629194869529218659252537680431806320 336
UVM_ERROR @ 6182.919420 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M
UVM_INFO @ 6182.919420 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---