Simulation Results: clkmgr

 
12/08/2026 15:30:28 DVSim: v1.50.1 sha: 71b9f97 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 91.15 %
  • code
  • 97.03 %
  • assert
  • 92.37 %
  • func
  • 84.05 %
  • line
  • 98.59 %
  • branch
  • 98.01 %
  • cond
  • 89.50 %
  • toggle
  • 99.03 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
75.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 0.830s 58.098us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 0.810s 29.898us 1 1 100.00
csr_rw 1 1 100.00
clkmgr_csr_rw 0.830s 57.461us 1 1 100.00
csr_bit_bash 1 1 100.00
clkmgr_csr_bit_bash 3.550s 761.900us 1 1 100.00
csr_aliasing 1 1 100.00
clkmgr_csr_aliasing 1.680s 242.594us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
clkmgr_csr_mem_rw_with_rand_reset 1.090s 123.873us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
clkmgr_csr_rw 0.830s 57.461us 1 1 100.00
clkmgr_csr_aliasing 1.680s 242.594us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 0.830s 30.437us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 1.540s 254.743us 1 1 100.00
extclk 1 1 100.00
clkmgr_extclk 0.990s 82.351us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 0.660s 16.160us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 0.830s 58.098us 1 1 100.00
frequency 1 1 100.00
clkmgr_frequency 9.210s 2499.041us 1 1 100.00
frequency_timeout 1 1 100.00
clkmgr_frequency_timeout 1.840s 281.798us 1 1 100.00
frequency_overflow 1 1 100.00
clkmgr_frequency 9.210s 2499.041us 1 1 100.00
stress_all 1 1 100.00
clkmgr_stress_all 24.140s 12136.052us 1 1 100.00
alert_test 1 1 100.00
clkmgr_alert_test 0.740s 16.037us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 1.580s 215.824us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 1.580s 215.824us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
clkmgr_csr_hw_reset 0.810s 29.898us 1 1 100.00
clkmgr_csr_rw 0.830s 57.461us 1 1 100.00
clkmgr_csr_aliasing 1.680s 242.594us 1 1 100.00
clkmgr_same_csr_outstanding 1.070s 44.173us 1 1 100.00
tl_d_partial_access 4 4 100.00
clkmgr_csr_hw_reset 0.810s 29.898us 1 1 100.00
clkmgr_csr_rw 0.830s 57.461us 1 1 100.00
clkmgr_csr_aliasing 1.680s 242.594us 1 1 100.00
clkmgr_same_csr_outstanding 1.070s 44.173us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 1 2 50.00
clkmgr_sec_cm 0.630s 1.999us 0 1 0.00
clkmgr_tl_intg_err 4.140s 1302.308us 1 1 100.00
shadow_reg_update_error 0 1 0.00
clkmgr_shadow_reg_errors 336.940s 200000.000us 0 1 0.00
shadow_reg_read_clear_staged_value 0 1 0.00
clkmgr_shadow_reg_errors 336.940s 200000.000us 0 1 0.00
shadow_reg_storage_error 0 1 0.00
clkmgr_shadow_reg_errors 336.940s 200000.000us 0 1 0.00
shadowed_reset_glitch 0 1 0.00
clkmgr_shadow_reg_errors 336.940s 200000.000us 0 1 0.00
shadow_reg_update_error_with_csr_rw 0 1 0.00
clkmgr_shadow_reg_errors_with_csr_rw 1.110s 39.855us 0 1 0.00
sec_cm_bus_integrity 1 1 100.00
clkmgr_tl_intg_err 4.140s 1302.308us 1 1 100.00
sec_cm_meas_clk_bkgn_chk 1 1 100.00
clkmgr_frequency 9.210s 2499.041us 1 1 100.00
sec_cm_timeout_clk_bkgn_chk 1 1 100.00
clkmgr_frequency_timeout 1.840s 281.798us 1 1 100.00
sec_cm_meas_config_shadow 0 1 0.00
clkmgr_shadow_reg_errors 336.940s 200000.000us 0 1 0.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 1.030s 73.585us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
clkmgr_lc_ctrl_intersig_mubi 0.770s 46.719us 1 1 100.00
sec_cm_lc_ctrl_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_lc_clk_byp_req_intersig_mubi 0.720s 32.994us 1 1 100.00
sec_cm_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_clk_handshake_intersig_mubi 0.740s 61.256us 1 1 100.00
sec_cm_div_intersig_mubi 1 1 100.00
clkmgr_div_intersig_mubi 0.970s 51.441us 1 1 100.00
sec_cm_jitter_config_mubi 1 1 100.00
clkmgr_csr_rw 0.830s 57.461us 1 1 100.00
sec_cm_idle_ctr_redun 0 1 0.00
clkmgr_sec_cm 0.630s 1.999us 0 1 0.00
sec_cm_meas_config_regwen 1 1 100.00
clkmgr_csr_rw 0.830s 57.461us 1 1 100.00
sec_cm_clk_ctrl_config_regwen 1 1 100.00
clkmgr_csr_rw 0.830s 57.461us 1 1 100.00
prim_count_check 0 1 0.00
clkmgr_sec_cm 0.630s 1.999us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 1 1 100.00
clkmgr_regwen 2.990s 713.939us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
clkmgr_stress_all_with_rand_reset 21.040s 1792.327us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 1 test run
clkmgr_shadow_reg_errors 77304098913854204805316800757315050834683987165996938667735576437598178296720 81
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_common_vseq.sv:50) [clkmgr_common_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == * (* [*] vs * [*]) fatal error fatal_fault does not trigger! 1 test run
clkmgr_shadow_reg_errors_with_csr_rw 95144540657846277765497169512796488313079815746375749962815204626623483081989 81
UVM_INFO @ 39855395 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1047) virtual_sequencer [clkmgr_common_vseq] Expected alert (fatal_fault) did not fire in * cycles. 1 test run
clkmgr_sec_cm 34457310898493304121770186923867522958216897562664420163204784915768551261593 84
UVM_INFO @ 1999295 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---