Simulation Results: csrng

 
12/08/2026 15:30:28 DVSim: v1.50.1 sha: 71b9f97 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 75.95 %
  • code
  • 88.16 %
  • assert
  • 92.79 %
  • func
  • 46.89 %
  • block
  • 94.85 %
  • line
  • 95.56 %
  • branch
  • 87.64 %
  • toggle
  • 83.71 %
  • FSM
  • 85.71 %
Validation stages
V1
100.00%
V2
83.33%
V2S
87.50%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
csrng_smoke 2.000s 23.809us 1 1 100.00
csr_hw_reset 1 1 100.00
csrng_csr_hw_reset 1.000s 16.428us 1 1 100.00
csr_rw 1 1 100.00
csrng_csr_rw 1.000s 29.784us 1 1 100.00
csr_bit_bash 1 1 100.00
csrng_csr_bit_bash 14.000s 585.865us 1 1 100.00
csr_aliasing 1 1 100.00
csrng_csr_aliasing 3.000s 54.351us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
csrng_csr_mem_rw_with_rand_reset 2.000s 41.042us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
csrng_csr_rw 1.000s 29.784us 1 1 100.00
csrng_csr_aliasing 3.000s 54.351us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
interrupts 1 1 100.00
csrng_intr 3.000s 48.286us 1 1 100.00
alerts 1 1 100.00
csrng_alert 6.000s 121.309us 1 1 100.00
err 1 1 100.00
csrng_err 2.000s 21.403us 1 1 100.00
cmds 0 1 0.00
csrng_cmds 10.000s 810.017us 0 1 0.00
life cycle 0 1 0.00
csrng_cmds 10.000s 810.017us 0 1 0.00
stress_all 0 1 0.00
csrng_stress_all 55.000s 1943.772us 0 1 0.00
intr_test 1 1 100.00
csrng_intr_test 2.000s 17.161us 1 1 100.00
alert_test 1 1 100.00
csrng_alert_test 2.000s 57.925us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
csrng_tl_errors 6.000s 176.758us 1 1 100.00
tl_d_illegal_access 1 1 100.00
csrng_tl_errors 6.000s 176.758us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
csrng_csr_hw_reset 1.000s 16.428us 1 1 100.00
csrng_csr_rw 1.000s 29.784us 1 1 100.00
csrng_csr_aliasing 3.000s 54.351us 1 1 100.00
csrng_same_csr_outstanding 4.000s 186.972us 1 1 100.00
tl_d_partial_access 4 4 100.00
csrng_csr_hw_reset 1.000s 16.428us 1 1 100.00
csrng_csr_rw 1.000s 29.784us 1 1 100.00
csrng_csr_aliasing 3.000s 54.351us 1 1 100.00
csrng_same_csr_outstanding 4.000s 186.972us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
csrng_sec_cm 5.000s 241.367us 1 1 100.00
csrng_tl_intg_err 3.000s 64.208us 1 1 100.00
sec_cm_config_regwen 2 2 100.00
csrng_regwen 2.000s 25.459us 1 1 100.00
csrng_csr_rw 1.000s 29.784us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
csrng_alert 6.000s 121.309us 1 1 100.00
sec_cm_intersig_mubi 0 1 0.00
csrng_stress_all 55.000s 1943.772us 0 1 0.00
sec_cm_main_sm_fsm_sparse 3 3 100.00
csrng_intr 3.000s 48.286us 1 1 100.00
csrng_err 2.000s 21.403us 1 1 100.00
csrng_sec_cm 5.000s 241.367us 1 1 100.00
sec_cm_cmd_stage_fsm_sparse 3 3 100.00
csrng_intr 3.000s 48.286us 1 1 100.00
csrng_err 2.000s 21.403us 1 1 100.00
csrng_sec_cm 5.000s 241.367us 1 1 100.00
sec_cm_ctr_drbg_fsm_sparse 3 3 100.00
csrng_intr 3.000s 48.286us 1 1 100.00
csrng_err 2.000s 21.403us 1 1 100.00
csrng_sec_cm 5.000s 241.367us 1 1 100.00
sec_cm_ctr_drbg_ctr_redun 3 3 100.00
csrng_intr 3.000s 48.286us 1 1 100.00
csrng_err 2.000s 21.403us 1 1 100.00
csrng_sec_cm 5.000s 241.367us 1 1 100.00
sec_cm_gen_cmd_ctr_redun 3 3 100.00
csrng_intr 3.000s 48.286us 1 1 100.00
csrng_err 2.000s 21.403us 1 1 100.00
csrng_sec_cm 5.000s 241.367us 1 1 100.00
sec_cm_ctrl_mubi 1 1 100.00
csrng_alert 6.000s 121.309us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
csrng_intr 3.000s 48.286us 1 1 100.00
csrng_err 2.000s 21.403us 1 1 100.00
sec_cm_constants_lc_gated 0 1 0.00
csrng_stress_all 55.000s 1943.772us 0 1 0.00
sec_cm_sw_genbits_bus_consistency 1 1 100.00
csrng_alert 6.000s 121.309us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
csrng_tl_intg_err 3.000s 64.208us 1 1 100.00
sec_cm_aes_cipher_fsm_sparse 3 3 100.00
csrng_intr 3.000s 48.286us 1 1 100.00
csrng_err 2.000s 21.403us 1 1 100.00
csrng_sec_cm 5.000s 241.367us 1 1 100.00
sec_cm_aes_cipher_fsm_redun 2 2 100.00
csrng_intr 3.000s 48.286us 1 1 100.00
csrng_err 2.000s 21.403us 1 1 100.00
sec_cm_aes_cipher_ctrl_sparse 2 2 100.00
csrng_intr 3.000s 48.286us 1 1 100.00
csrng_err 2.000s 21.403us 1 1 100.00
sec_cm_aes_cipher_fsm_local_esc 2 2 100.00
csrng_intr 3.000s 48.286us 1 1 100.00
csrng_err 2.000s 21.403us 1 1 100.00
sec_cm_aes_cipher_ctr_redun 3 3 100.00
csrng_intr 3.000s 48.286us 1 1 100.00
csrng_err 2.000s 21.403us 1 1 100.00
csrng_sec_cm 5.000s 241.367us 1 1 100.00
sec_cm_aes_cipher_data_reg_local_esc 2 2 100.00
csrng_intr 3.000s 48.286us 1 1 100.00
csrng_err 2.000s 21.403us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
csrng_stress_all_with_rand_reset 5.000s 196.929us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (csrng_scoreboard.sv:177) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq 2 test runs
csrng_stress_all 80993143948952413034779870788209978105163443248163906352295419365380086378273 114
UVM_INFO @ 1943771815 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_stress_all_with_rand_reset 107076179558819995971192056241512103765460278635742766072388042524098240978580 108
UVM_INFO @ 196929329 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csrng_scoreboard.sv:429) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: csrng_reg_block.genbits 1 test run
csrng_cmds 62680782096545862668506261705887105314943087224564805617176607849672298805971 103
UVM_INFO @ 810017494 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---