Simulation Results: edn/edn0

 
12/08/2026 15:30:28 DVSim: v1.50.1 sha: 71b9f97 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 84.83 %
  • code
  • 79.61 %
  • assert
  • 96.31 %
  • func
  • 78.57 %
  • line
  • 97.17 %
  • branch
  • 89.96 %
  • cond
  • 82.94 %
  • toggle
  • 74.76 %
  • FSM
  • 53.23 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.860s 18.848us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.770s 16.668us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.890s 39.624us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 2.720s 85.143us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.410s 43.265us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.190s 23.296us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.890s 39.624us 1 1 100.00
edn_csr_aliasing 1.410s 43.265us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.340s 42.221us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.340s 42.221us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.340s 42.221us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.920s 22.916us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.180s 129.370us 1 1 100.00
errs 1 1 100.00
edn_err 0.920s 19.592us 1 1 100.00
disable 2 2 100.00
edn_disable 0.970s 13.898us 1 1 100.00
edn_disable_auto_req_mode 0.930s 108.182us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 2.280s 630.596us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.900s 13.458us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.920s 17.592us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 1.850s 113.672us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 1.850s 113.672us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.770s 16.668us 1 1 100.00
edn_csr_rw 0.890s 39.624us 1 1 100.00
edn_csr_aliasing 1.410s 43.265us 1 1 100.00
edn_same_csr_outstanding 1.120s 63.650us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.770s 16.668us 1 1 100.00
edn_csr_rw 0.890s 39.624us 1 1 100.00
edn_csr_aliasing 1.410s 43.265us 1 1 100.00
edn_same_csr_outstanding 1.120s 63.650us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 3.820s 1050.414us 1 1 100.00
edn_tl_intg_err 1.300s 93.706us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.800s 88.779us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.180s 129.370us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 3.820s 1050.414us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 3.820s 1050.414us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 3.820s 1050.414us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 3.820s 1050.414us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.180s 129.370us 1 1 100.00
edn_sec_cm 3.820s 1050.414us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.180s 129.370us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.300s 93.706us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
edn_stress_all_with_rand_reset 21.870s 1167.496us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1286) [edn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
edn_stress_all_with_rand_reset 47054370428039387927878696187034846767893015773123994610952448776680649753478 147
UVM_INFO @ 1167496395 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---