Simulation Results: edn/edn1

 
12/08/2026 15:30:28 DVSim: v1.50.1 sha: 71b9f97 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 87.80 %
  • code
  • 81.78 %
  • assert
  • 98.44 %
  • func
  • 83.19 %
  • line
  • 97.80 %
  • branch
  • 92.64 %
  • cond
  • 89.85 %
  • toggle
  • 87.68 %
  • FSM
  • 40.91 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.850s 21.227us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.770s 18.189us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.740s 22.582us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 2.570s 88.012us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 0.920s 50.911us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.090s 51.171us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.740s 22.582us 1 1 100.00
edn_csr_aliasing 0.920s 50.911us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.050s 41.235us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.050s 41.235us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.050s 41.235us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.740s 36.498us 1 1 100.00
alerts 1 1 100.00
edn_alert 0.910s 73.808us 1 1 100.00
errs 1 1 100.00
edn_err 0.820s 33.961us 1 1 100.00
disable 2 2 100.00
edn_disable 0.800s 13.790us 1 1 100.00
edn_disable_auto_req_mode 0.930s 36.168us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 4.290s 2908.237us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.740s 39.524us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.770s 47.397us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 2.770s 921.599us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 2.770s 921.599us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.770s 18.189us 1 1 100.00
edn_csr_rw 0.740s 22.582us 1 1 100.00
edn_csr_aliasing 0.920s 50.911us 1 1 100.00
edn_same_csr_outstanding 0.880s 69.166us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.770s 18.189us 1 1 100.00
edn_csr_rw 0.740s 22.582us 1 1 100.00
edn_csr_aliasing 0.920s 50.911us 1 1 100.00
edn_same_csr_outstanding 0.880s 69.166us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 2.300s 276.058us 1 1 100.00
edn_tl_intg_err 1.340s 59.297us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.810s 20.356us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 0.910s 73.808us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 2.300s 276.058us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 2.300s 276.058us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 2.300s 276.058us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 2.300s 276.058us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 0.910s 73.808us 1 1 100.00
edn_sec_cm 2.300s 276.058us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 0.910s 73.808us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.340s 59.297us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 26.300s 7421.659us 1 1 100.00