Simulation Results: entropy_src/rng_4bits

 
12/08/2026 15:30:28 DVSim: v1.50.1 sha: 71b9f97 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 75.05 %
  • code
  • 88.48 %
  • assert
  • 84.40 %
  • func
  • 52.26 %
  • block
  • 94.47 %
  • line
  • 97.14 %
  • branch
  • 86.64 %
  • toggle
  • 76.41 %
  • FSM
  • 93.75 %
Validation stages
V1
83.33%
V2
100.00%
V2S
100.00%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
entropy_src_smoke 2.000s 42.021us 1 1 100.00
csr_hw_reset 1 1 100.00
entropy_src_csr_hw_reset 2.000s 220.597us 1 1 100.00
csr_rw 1 1 100.00
entropy_src_csr_rw 1.000s 82.405us 1 1 100.00
csr_bit_bash 1 1 100.00
entropy_src_csr_bit_bash 7.000s 8066.733us 1 1 100.00
csr_aliasing 1 1 100.00
entropy_src_csr_aliasing 2.000s 75.342us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
entropy_src_csr_mem_rw_with_rand_reset 2.000s 69.319us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
entropy_src_csr_rw 1.000s 82.405us 1 1 100.00
entropy_src_csr_aliasing 2.000s 75.342us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 3 3 100.00
entropy_src_smoke 2.000s 42.021us 1 1 100.00
entropy_src_rng 63.000s 13387.605us 1 1 100.00
entropy_src_fw_ov 72.000s 14212.593us 1 1 100.00
firmware_mode 1 1 100.00
entropy_src_fw_ov 72.000s 14212.593us 1 1 100.00
rng_mode 1 1 100.00
entropy_src_rng 63.000s 13387.605us 1 1 100.00
rng_max_rate 1 1 100.00
entropy_src_rng_max_rate 351.000s 13058.047us 1 1 100.00
health_checks 1 1 100.00
entropy_src_rng 63.000s 13387.605us 1 1 100.00
conditioning 1 1 100.00
entropy_src_rng 63.000s 13387.605us 1 1 100.00
interrupts 2 2 100.00
entropy_src_rng 63.000s 13387.605us 1 1 100.00
entropy_src_intr 8.000s 527.263us 1 1 100.00
alerts 2 2 100.00
entropy_src_rng 63.000s 13387.605us 1 1 100.00
entropy_src_functional_alerts 4.000s 965.624us 1 1 100.00
stress_all 1 1 100.00
entropy_src_stress_all 2.000s 107.557us 1 1 100.00
functional_errors 1 1 100.00
entropy_src_functional_errors 2.000s 86.228us 1 1 100.00
firmware_ov_read_contiguous_data 1 1 100.00
entropy_src_fw_ov_contiguous 3.000s 58.636us 1 1 100.00
intr_test 1 1 100.00
entropy_src_intr_test 1.000s 26.468us 1 1 100.00
alert_test 1 1 100.00
entropy_src_alert_test 1.000s 30.944us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
entropy_src_tl_errors 2.000s 48.958us 1 1 100.00
tl_d_illegal_access 1 1 100.00
entropy_src_tl_errors 2.000s 48.958us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
entropy_src_csr_hw_reset 2.000s 220.597us 1 1 100.00
entropy_src_csr_rw 1.000s 82.405us 1 1 100.00
entropy_src_csr_aliasing 2.000s 75.342us 1 1 100.00
entropy_src_same_csr_outstanding 3.000s 265.704us 1 1 100.00
tl_d_partial_access 4 4 100.00
entropy_src_csr_hw_reset 2.000s 220.597us 1 1 100.00
entropy_src_csr_rw 1.000s 82.405us 1 1 100.00
entropy_src_csr_aliasing 2.000s 75.342us 1 1 100.00
entropy_src_same_csr_outstanding 3.000s 265.704us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
entropy_src_sec_cm 2.000s 102.949us 1 1 100.00
entropy_src_tl_intg_err 2.000s 184.774us 1 1 100.00
sec_cm_config_regwen 2 2 100.00
entropy_src_rng 63.000s 13387.605us 1 1 100.00
entropy_src_cfg_regwen 1.000s 44.070us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
entropy_src_rng 63.000s 13387.605us 1 1 100.00
sec_cm_config_redun 1 1 100.00
entropy_src_rng 63.000s 13387.605us 1 1 100.00
sec_cm_intersig_mubi 2 2 100.00
entropy_src_rng 63.000s 13387.605us 1 1 100.00
entropy_src_fw_ov 72.000s 14212.593us 1 1 100.00
sec_cm_main_sm_fsm_sparse 2 2 100.00
entropy_src_functional_errors 2.000s 86.228us 1 1 100.00
entropy_src_sec_cm 2.000s 102.949us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 2 2 100.00
entropy_src_functional_errors 2.000s 86.228us 1 1 100.00
entropy_src_sec_cm 2.000s 102.949us 1 1 100.00
sec_cm_rng_bkgn_chk 1 1 100.00
entropy_src_rng 63.000s 13387.605us 1 1 100.00
sec_cm_fifo_ctr_redun 2 2 100.00
entropy_src_functional_errors 2.000s 86.228us 1 1 100.00
entropy_src_sec_cm 2.000s 102.949us 1 1 100.00
sec_cm_ctr_redun 2 2 100.00
entropy_src_functional_errors 2.000s 86.228us 1 1 100.00
entropy_src_sec_cm 2.000s 102.949us 1 1 100.00
sec_cm_ctr_local_esc 1 1 100.00
entropy_src_functional_errors 2.000s 86.228us 1 1 100.00
sec_cm_esfinal_rdata_bus_consistency 1 1 100.00
entropy_src_functional_alerts 4.000s 965.624us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
entropy_src_tl_intg_err 2.000s 184.774us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
external_health_tests 1 1 100.00
entropy_src_rng_with_xht_rsps 28.000s 13129.465us 1 1 100.00
stress_all_with_rand_reset 0 1 0.00
entropy_src_stress_all_with_rand_reset 3.000s 61.439us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL sequencer [SEQDEFPRI] Sequence parent_sequence has illegal priority: -* 1 test run
entropy_src_stress_all_with_rand_reset 48900957330149376535368828377509114479147688867694969494882127573541571127832 121
UVM_INFO @ 61438872 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (entropy_src_base_vseq.sv:83) virtual_sequencer [mirror] Failed to mirror alert_fail_counts 1 test run
entropy_src_csr_mem_rw_with_rand_reset 87793432939970317832490523301714824869145663747532969665440837352114721434591 113
UVM_INFO @ 69318704 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---