Simulation Results: flash_ctrl

 
12/08/2026 15:30:28 DVSim: v1.50.1 sha: 71b9f97 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.49 %
  • code
  • 93.85 %
  • assert
  • 96.94 %
  • func
  • 95.67 %
  • line
  • 95.93 %
  • branch
  • 97.12 %
  • cond
  • 93.71 %
  • toggle
  • 95.42 %
  • FSM
  • 87.07 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
flash_ctrl_smoke 68.430s 219.885us 1 1 100.00
smoke_hw 1 1 100.00
flash_ctrl_smoke_hw 11.300s 31.654us 1 1 100.00
csr_hw_reset 1 1 100.00
flash_ctrl_csr_hw_reset 22.030s 95.695us 1 1 100.00
csr_rw 1 1 100.00
flash_ctrl_csr_rw 8.130s 62.498us 1 1 100.00
csr_bit_bash 1 1 100.00
flash_ctrl_csr_bit_bash 53.980s 3668.232us 1 1 100.00
csr_aliasing 1 1 100.00
flash_ctrl_csr_aliasing 40.310s 1509.624us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
flash_ctrl_csr_mem_rw_with_rand_reset 9.680s 98.823us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
flash_ctrl_csr_rw 8.130s 62.498us 1 1 100.00
flash_ctrl_csr_aliasing 40.310s 1509.624us 1 1 100.00
mem_walk 1 1 100.00
flash_ctrl_mem_walk 7.220s 203.854us 1 1 100.00
mem_partial_access 1 1 100.00
flash_ctrl_mem_partial_access 6.120s 61.801us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sw_op 1 1 100.00
flash_ctrl_sw_op 17.730s 79.047us 1 1 100.00
host_read_direct 1 1 100.00
flash_ctrl_host_dir_rd 20.420s 66.671us 1 1 100.00
rma_hw_if 3 3 100.00
flash_ctrl_hw_rma 1101.920s 85463.445us 1 1 100.00
flash_ctrl_hw_rma_reset 1088.440s 760643.449us 1 1 100.00
flash_ctrl_lcmgr_intg 8.620s 86.281us 1 1 100.00
host_controller_arb 1 1 100.00
flash_ctrl_host_ctrl_arb 951.550s 313929.398us 1 1 100.00
erase_suspend 1 1 100.00
flash_ctrl_erase_suspend 160.510s 2867.022us 1 1 100.00
program_reset 1 1 100.00
flash_ctrl_prog_reset 6.040s 72.217us 1 1 100.00
full_memory_access 1 1 100.00
flash_ctrl_full_mem_access 1645.110s 203596.275us 1 1 100.00
rd_buff_eviction 1 1 100.00
flash_ctrl_rd_buff_evict 62.230s 6959.057us 1 1 100.00
rd_buff_eviction_w_ecc 3 3 100.00
flash_ctrl_rw_evict 15.430s 35.673us 1 1 100.00
flash_ctrl_rw_evict_all_en 13.200s 332.359us 1 1 100.00
flash_ctrl_re_evict 16.430s 217.273us 1 1 100.00
host_arb 1 1 100.00
flash_ctrl_phy_arb 166.780s 2381.612us 1 1 100.00
host_interleave 1 1 100.00
flash_ctrl_phy_arb 166.780s 2381.612us 1 1 100.00
memory_protection 1 1 100.00
flash_ctrl_mp_regions 252.550s 19575.763us 1 1 100.00
fetch_code 1 1 100.00
flash_ctrl_fetch_code 14.480s 420.610us 1 1 100.00
all_partitions 1 1 100.00
flash_ctrl_rand_ops 446.310s 3683.341us 1 1 100.00
error_mp 1 1 100.00
flash_ctrl_error_mp 400.910s 6006.661us 1 1 100.00
error_prog_win 1 1 100.00
flash_ctrl_error_prog_win 302.660s 1168.027us 1 1 100.00
error_prog_type 1 1 100.00
flash_ctrl_error_prog_type 894.590s 2007.117us 1 1 100.00
error_read_seed 1 1 100.00
flash_ctrl_hw_read_seed_err 6.270s 81.098us 1 1 100.00
read_write_overflow 1 1 100.00
flash_ctrl_oversize_error 96.090s 3084.590us 1 1 100.00
flash_ctrl_disable 1 1 100.00
flash_ctrl_disable 10.850s 39.845us 1 1 100.00
flash_ctrl_connect 1 1 100.00
flash_ctrl_connect 7.530s 26.424us 1 1 100.00
stress_all 1 1 100.00
flash_ctrl_stress_all 71.570s 63.697us 1 1 100.00
secret_partition 2 2 100.00
flash_ctrl_hw_sec_otp 84.200s 18241.093us 1 1 100.00
flash_ctrl_otp_reset 60.430s 47.779us 1 1 100.00
isolation_partition 1 1 100.00
flash_ctrl_hw_rma 1101.920s 85463.445us 1 1 100.00
interrupts 4 4 100.00
flash_ctrl_intr_rd 133.000s 5781.817us 1 1 100.00
flash_ctrl_intr_wr 49.660s 5918.909us 1 1 100.00
flash_ctrl_intr_rd_slow_flash 76.780s 97376.672us 1 1 100.00
flash_ctrl_intr_wr_slow_flash 106.910s 43062.926us 1 1 100.00
invalid_op 1 1 100.00
flash_ctrl_invalid_op 47.970s 4168.694us 1 1 100.00
mid_op_rst 1 1 100.00
flash_ctrl_mid_op_rst 36.820s 1797.228us 1 1 100.00
double_bit_err 5 5 100.00
flash_ctrl_read_word_sweep_derr 9.890s 47.081us 1 1 100.00
flash_ctrl_ro_derr 98.230s 1435.418us 1 1 100.00
flash_ctrl_rw_derr 147.260s 7439.823us 1 1 100.00
flash_ctrl_derr_detect 99.220s 2941.169us 1 1 100.00
flash_ctrl_integrity 364.760s 42517.176us 1 1 100.00
single_bit_err 3 3 100.00
flash_ctrl_read_word_sweep_serr 12.040s 102.383us 1 1 100.00
flash_ctrl_ro_serr 106.180s 3420.269us 1 1 100.00
flash_ctrl_rw_serr 157.820s 4004.083us 1 1 100.00
singlebit_err_counter 1 1 100.00
flash_ctrl_serr_counter 41.450s 937.326us 1 1 100.00
singlebit_err_address 1 1 100.00
flash_ctrl_serr_address 56.840s 1170.648us 1 1 100.00
scramble 5 5 100.00
flash_ctrl_wo 73.600s 1783.101us 1 1 100.00
flash_ctrl_write_word_sweep 7.650s 77.638us 1 1 100.00
flash_ctrl_read_word_sweep 6.620s 101.214us 1 1 100.00
flash_ctrl_ro 93.150s 2819.062us 1 1 100.00
flash_ctrl_rw 445.800s 7041.514us 1 1 100.00
filesystem_support 1 1 100.00
flash_ctrl_fs_sup 21.630s 779.737us 1 1 100.00
rma_write_process_error 2 2 100.00
flash_ctrl_rma_err 573.580s 82293.692us 1 1 100.00
flash_ctrl_hw_prog_rma_wipe_err 20.920s 10095.815us 1 1 100.00
alert_test 1 1 100.00
flash_ctrl_alert_test 6.540s 144.612us 1 1 100.00
intr_test 1 1 100.00
flash_ctrl_intr_test 5.780s 73.398us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
flash_ctrl_tl_errors 8.400s 73.181us 1 1 100.00
tl_d_illegal_access 1 1 100.00
flash_ctrl_tl_errors 8.400s 73.181us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
flash_ctrl_csr_hw_reset 22.030s 95.695us 1 1 100.00
flash_ctrl_csr_rw 8.130s 62.498us 1 1 100.00
flash_ctrl_csr_aliasing 40.310s 1509.624us 1 1 100.00
flash_ctrl_same_csr_outstanding 15.680s 38.667us 1 1 100.00
tl_d_partial_access 4 4 100.00
flash_ctrl_csr_hw_reset 22.030s 95.695us 1 1 100.00
flash_ctrl_csr_rw 8.130s 62.498us 1 1 100.00
flash_ctrl_csr_aliasing 40.310s 1509.624us 1 1 100.00
flash_ctrl_same_csr_outstanding 15.680s 38.667us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
flash_ctrl_shadow_reg_errors 28.370s 27.556us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
flash_ctrl_shadow_reg_errors 28.370s 27.556us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
flash_ctrl_shadow_reg_errors 28.370s 27.556us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
flash_ctrl_shadow_reg_errors 28.370s 27.556us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
flash_ctrl_shadow_reg_errors_with_csr_rw 23.820s 599.164us 1 1 100.00
tl_intg_err 2 2 100.00
flash_ctrl_sec_cm 1715.220s 8295.507us 1 1 100.00
flash_ctrl_tl_intg_err 422.020s 3156.929us 1 1 100.00
sec_cm_reg_bus_integrity 1 1 100.00
flash_ctrl_tl_intg_err 422.020s 3156.929us 1 1 100.00
sec_cm_host_bus_integrity 1 1 100.00
flash_ctrl_tl_intg_err 422.020s 3156.929us 1 1 100.00
sec_cm_mem_bus_integrity 2 2 100.00
flash_ctrl_rd_intg 16.150s 74.658us 1 1 100.00
flash_ctrl_wr_intg 8.850s 192.435us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
flash_ctrl_smoke 68.430s 219.885us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 4 4 100.00
flash_ctrl_otp_reset 60.430s 47.779us 1 1 100.00
flash_ctrl_disable 10.850s 39.845us 1 1 100.00
flash_ctrl_sec_info_access 32.720s 1909.642us 1 1 100.00
flash_ctrl_connect 7.530s 26.424us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
flash_ctrl_config_regwen 6.130s 83.875us 1 1 100.00
sec_cm_data_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 8.130s 62.498us 1 1 100.00
sec_cm_data_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 28.370s 27.556us 1 1 100.00
sec_cm_info_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 8.130s 62.498us 1 1 100.00
sec_cm_info_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 28.370s 27.556us 1 1 100.00
sec_cm_bank_config_regwen 1 1 100.00
flash_ctrl_csr_rw 8.130s 62.498us 1 1 100.00
sec_cm_bank_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 28.370s 27.556us 1 1 100.00
sec_cm_mem_ctrl_global_esc 1 1 100.00
flash_ctrl_disable 10.850s 39.845us 1 1 100.00
sec_cm_mem_ctrl_local_esc 2 2 100.00
flash_ctrl_rd_intg 16.150s 74.658us 1 1 100.00
flash_ctrl_access_after_disable 6.080s 36.241us 1 1 100.00
sec_cm_mem_addr_infection 1 1 100.00
flash_ctrl_host_addr_infection 15.440s 66.072us 1 1 100.00
sec_cm_mem_disable_config_mubi 1 1 100.00
flash_ctrl_disable 10.850s 39.845us 1 1 100.00
sec_cm_exec_config_redun 1 1 100.00
flash_ctrl_fetch_code 14.480s 420.610us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
flash_ctrl_rw 445.800s 7041.514us 1 1 100.00
sec_cm_mem_integrity 3 3 100.00
flash_ctrl_rw_serr 157.820s 4004.083us 1 1 100.00
flash_ctrl_rw_derr 147.260s 7439.823us 1 1 100.00
flash_ctrl_integrity 364.760s 42517.176us 1 1 100.00
sec_cm_rma_entry_mem_sec_wipe 1 1 100.00
flash_ctrl_hw_rma 1101.920s 85463.445us 1 1 100.00
sec_cm_ctrl_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1715.220s 8295.507us 1 1 100.00
sec_cm_phy_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1715.220s 8295.507us 1 1 100.00
sec_cm_phy_prog_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1715.220s 8295.507us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
flash_ctrl_sec_cm 1715.220s 8295.507us 1 1 100.00
sec_cm_phy_arbiter_ctrl_redun 1 1 100.00
flash_ctrl_phy_arb_redun 12.440s 935.777us 1 1 100.00
sec_cm_phy_host_grant_ctrl_consistency 1 1 100.00
flash_ctrl_phy_host_grant_err 6.450s 35.333us 1 1 100.00
sec_cm_phy_ack_ctrl_consistency 1 1 100.00
flash_ctrl_phy_ack_consistency 6.250s 38.567us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
flash_ctrl_sec_cm 1715.220s 8295.507us 1 1 100.00
sec_cm_mem_tl_lc_gate_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1715.220s 8295.507us 1 1 100.00
sec_cm_prog_tl_lc_gate_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1715.220s 8295.507us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
asymmetric_read_path 1 1 100.00
flash_ctrl_rd_ooo 21.830s 184.326us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
flash_ctrl_basic_rw 246.780s 625.781us 1 1 100.00