Simulation Results: hmac

 
12/08/2026 15:30:28 DVSim: v1.50.1 sha: 71b9f97 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 79.46 %
  • code
  • 97.79 %
  • assert
  • 97.60 %
  • func
  • 43.00 %
  • line
  • 99.74 %
  • branch
  • 99.17 %
  • cond
  • 95.90 %
  • toggle
  • 100.00 %
  • FSM
  • 94.12 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 2.750s 3062.911us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 0.830s 20.337us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 0.950s 32.920us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 4.110s 166.704us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 2.500s 1706.237us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 1.500s 225.804us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 0.950s 32.920us 1 1 100.00
hmac_csr_aliasing 2.500s 1706.237us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 65.570s 9805.187us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 4.340s 1516.092us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 253.300s 16821.674us 1 1 100.00
hmac_test_sha384_vectors 19.520s 1177.520us 1 1 100.00
hmac_test_sha512_vectors 356.310s 18143.140us 1 1 100.00
hmac_test_hmac256_vectors 10.140s 1672.750us 1 1 100.00
hmac_test_hmac384_vectors 7.420s 1157.303us 1 1 100.00
hmac_test_hmac512_vectors 10.590s 395.481us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 15.650s 6643.076us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 783.610s 8530.695us 1 1 100.00
error 1 1 100.00
hmac_error 30.120s 1025.865us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 30.460s 3166.107us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 2.750s 3062.911us 1 1 100.00
hmac_long_msg 65.570s 9805.187us 1 1 100.00
hmac_back_pressure 4.340s 1516.092us 1 1 100.00
hmac_datapath_stress 783.610s 8530.695us 1 1 100.00
hmac_burst_wr 15.650s 6643.076us 1 1 100.00
hmac_stress_all 35.640s 4663.980us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 2.750s 3062.911us 1 1 100.00
hmac_long_msg 65.570s 9805.187us 1 1 100.00
hmac_back_pressure 4.340s 1516.092us 1 1 100.00
hmac_datapath_stress 783.610s 8530.695us 1 1 100.00
hmac_wipe_secret 30.460s 3166.107us 1 1 100.00
hmac_test_sha256_vectors 253.300s 16821.674us 1 1 100.00
hmac_test_sha384_vectors 19.520s 1177.520us 1 1 100.00
hmac_test_sha512_vectors 356.310s 18143.140us 1 1 100.00
hmac_test_hmac256_vectors 10.140s 1672.750us 1 1 100.00
hmac_test_hmac384_vectors 7.420s 1157.303us 1 1 100.00
hmac_test_hmac512_vectors 10.590s 395.481us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 2.750s 3062.911us 1 1 100.00
hmac_long_msg 65.570s 9805.187us 1 1 100.00
hmac_back_pressure 4.340s 1516.092us 1 1 100.00
hmac_datapath_stress 783.610s 8530.695us 1 1 100.00
hmac_burst_wr 15.650s 6643.076us 1 1 100.00
hmac_error 30.120s 1025.865us 1 1 100.00
hmac_wipe_secret 30.460s 3166.107us 1 1 100.00
hmac_test_sha256_vectors 253.300s 16821.674us 1 1 100.00
hmac_test_sha384_vectors 19.520s 1177.520us 1 1 100.00
hmac_test_sha512_vectors 356.310s 18143.140us 1 1 100.00
hmac_test_hmac256_vectors 10.140s 1672.750us 1 1 100.00
hmac_test_hmac384_vectors 7.420s 1157.303us 1 1 100.00
hmac_test_hmac512_vectors 10.590s 395.481us 1 1 100.00
hmac_stress_all 35.640s 4663.980us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 35.640s 4663.980us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 0.600s 40.761us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 0.720s 23.351us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 1.390s 289.497us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 1.390s 289.497us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 0.830s 20.337us 1 1 100.00
hmac_csr_rw 0.950s 32.920us 1 1 100.00
hmac_csr_aliasing 2.500s 1706.237us 1 1 100.00
hmac_same_csr_outstanding 1.470s 95.355us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 0.830s 20.337us 1 1 100.00
hmac_csr_rw 0.950s 32.920us 1 1 100.00
hmac_csr_aliasing 2.500s 1706.237us 1 1 100.00
hmac_same_csr_outstanding 1.470s 95.355us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 0.810s 235.570us 1 1 100.00
hmac_tl_intg_err 1.680s 371.429us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 1.680s 371.429us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 2.750s 3062.911us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 4.670s 429.891us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 23.510s 3293.188us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 0.810s 43.697us 1 1 100.00