Simulation Results: i2c

 
12/08/2026 15:30:28 DVSim: v1.50.1 sha: 71b9f97 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 85.83 %
  • code
  • 78.53 %
  • assert
  • 97.04 %
  • func
  • 81.92 %
  • line
  • 96.44 %
  • branch
  • 92.41 %
  • cond
  • 85.12 %
  • toggle
  • 74.04 %
  • FSM
  • 44.64 %
Validation stages
V1
100.00%
V2
92.68%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
host_smoke 1 1 100.00
i2c_host_smoke 24.000s 4245.345us 1 1 100.00
target_smoke 1 1 100.00
i2c_target_smoke 19.160s 2040.660us 1 1 100.00
csr_hw_reset 1 1 100.00
i2c_csr_hw_reset 0.640s 116.057us 1 1 100.00
csr_rw 1 1 100.00
i2c_csr_rw 0.700s 29.052us 1 1 100.00
csr_bit_bash 1 1 100.00
i2c_csr_bit_bash 2.510s 378.578us 1 1 100.00
csr_aliasing 1 1 100.00
i2c_csr_aliasing 1.240s 60.154us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
i2c_csr_mem_rw_with_rand_reset 0.870s 339.342us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
i2c_csr_rw 0.700s 29.052us 1 1 100.00
i2c_csr_aliasing 1.240s 60.154us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
host_error_intr 0 1 0.00
i2c_host_error_intr 0.930s 33.363us 0 1 0.00
host_stress_all 0 1 0.00
i2c_host_stress_all 0.920s 255.910us 0 1 0.00
host_maxperf 1 1 100.00
i2c_host_perf 26.940s 5633.234us 1 1 100.00
host_override 1 1 100.00
i2c_host_override 0.940s 115.677us 1 1 100.00
host_fifo_watermark 1 1 100.00
i2c_host_fifo_watermark 36.550s 2882.336us 1 1 100.00
host_fifo_overflow 1 1 100.00
i2c_host_fifo_overflow 28.850s 7692.167us 1 1 100.00
host_fifo_reset 3 3 100.00
i2c_host_fifo_reset_fmt 1.280s 1445.955us 1 1 100.00
i2c_host_fifo_fmt_empty 8.690s 940.831us 1 1 100.00
i2c_host_fifo_reset_rx 2.450s 142.412us 1 1 100.00
host_fifo_full 1 1 100.00
i2c_host_fifo_full 59.980s 2491.278us 1 1 100.00
host_timeout 1 1 100.00
i2c_host_stretch_timeout 32.380s 5796.614us 1 1 100.00
i2c_host_mode_toggle 1 1 100.00
i2c_host_mode_toggle 4.370s 167.183us 1 1 100.00
target_glitch 0 1 0.00
i2c_target_glitch 1.760s 978.472us 0 1 0.00
target_stress_all 1 1 100.00
i2c_target_stress_all 1676.300s 87230.798us 1 1 100.00
target_maxperf 1 1 100.00
i2c_target_perf 3.700s 3999.043us 1 1 100.00
target_fifo_empty 2 2 100.00
i2c_target_stress_rd 24.160s 950.402us 1 1 100.00
i2c_target_intr_smoke 3.400s 1701.600us 1 1 100.00
target_fifo_reset 2 2 100.00
i2c_target_fifo_reset_acq 1.270s 239.159us 1 1 100.00
i2c_target_fifo_reset_tx 1.470s 787.974us 1 1 100.00
target_fifo_full 3 3 100.00
i2c_target_stress_wr 485.490s 67722.160us 1 1 100.00
i2c_target_stress_rd 24.160s 950.402us 1 1 100.00
i2c_target_intr_stress_wr 4.250s 9427.101us 1 1 100.00
target_timeout 1 1 100.00
i2c_target_timeout 4.590s 4716.531us 1 1 100.00
target_clock_stretch 1 1 100.00
i2c_target_stretch 1.220s 273.769us 1 1 100.00
bad_address 1 1 100.00
i2c_target_bad_addr 3.640s 4355.813us 1 1 100.00
target_mode_glitch 1 1 100.00
i2c_target_hrst 1.540s 1312.392us 1 1 100.00
target_fifo_watermark 2 2 100.00
i2c_target_fifo_watermarks_acq 2.230s 2030.210us 1 1 100.00
i2c_target_fifo_watermarks_tx 1.240s 425.337us 1 1 100.00
host_mode_config_perf 2 2 100.00
i2c_host_perf 26.940s 5633.234us 1 1 100.00
i2c_host_perf_precise 109.660s 6036.874us 1 1 100.00
host_mode_clock_stretching 1 1 100.00
i2c_host_stretch_timeout 32.380s 5796.614us 1 1 100.00
target_mode_tx_stretch_ctrl 1 1 100.00
i2c_target_tx_stretch_ctrl 3.810s 143.774us 1 1 100.00
target_mode_nack_generation 3 3 100.00
i2c_target_nack_acqfull 1.930s 2348.553us 1 1 100.00
i2c_target_nack_acqfull_addr 2.070s 533.275us 1 1 100.00
i2c_target_nack_txstretch 1.380s 703.907us 1 1 100.00
host_mode_halt_on_nak 1 1 100.00
i2c_host_may_nack 3.450s 590.962us 1 1 100.00
target_mode_smbus_maxlen 1 1 100.00
i2c_target_smbus_maxlen 1.500s 3865.466us 1 1 100.00
alert_test 1 1 100.00
i2c_alert_test 0.840s 58.842us 1 1 100.00
intr_test 1 1 100.00
i2c_intr_test 0.650s 22.161us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
i2c_tl_errors 1.520s 115.129us 1 1 100.00
tl_d_illegal_access 1 1 100.00
i2c_tl_errors 1.520s 115.129us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
i2c_csr_hw_reset 0.640s 116.057us 1 1 100.00
i2c_csr_rw 0.700s 29.052us 1 1 100.00
i2c_csr_aliasing 1.240s 60.154us 1 1 100.00
i2c_same_csr_outstanding 1.030s 96.256us 1 1 100.00
tl_d_partial_access 4 4 100.00
i2c_csr_hw_reset 0.640s 116.057us 1 1 100.00
i2c_csr_rw 0.700s 29.052us 1 1 100.00
i2c_csr_aliasing 1.240s 60.154us 1 1 100.00
i2c_same_csr_outstanding 1.030s 96.256us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
i2c_tl_intg_err 1.950s 716.838us 1 1 100.00
i2c_sec_cm 1.100s 104.753us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
i2c_tl_intg_err 1.950s 716.838us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
host_stress_all_with_rand_reset 0 1 0.00
i2c_host_stress_all_with_rand_reset 9.970s 4182.474us 0 1 0.00
target_error_intr 0 1 0.00
i2c_target_unexp_stop 2.090s 196.260us 0 1 0.00
target_stress_all_with_rand_reset 0 1 0.00
i2c_target_stress_all_with_rand_reset 18.670s 1823.614us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between 2 test runs
i2c_host_error_intr 51975796913087638820462310793714596937708024746673548459787454806579298922534 102
UVM_INFO @ 33363393 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
i2c_host_stress_all 33301674807157466469688029217310988851299539329712990567538766903749360911639 100
UVM_INFO @ 255909775 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1286) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 2 test runs
i2c_host_stress_all_with_rand_reset 77434943324235724326097068567213342519069904639160620355209968581097960466805 97
UVM_INFO @ 4182474236 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
i2c_target_stress_all_with_rand_reset 49188196208578585655398544471992113819063641494665697570736986908409268252717 97
UVM_INFO @ 1823614434 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between 1 test run
i2c_target_glitch 9301538304702032427901391439923830626497000926936059207336716643604350736903 90
UVM_INFO @ 978472499 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))' 1 test run
i2c_target_unexp_stop 38845228230184841663309070035183575889692032865276517571753567242697182653055 85
UVM_ERROR @ 196259559 ps: (i2c_fifos.sv:318) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 196259559 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---