Simulation Results: lc_ctrl/volatile_unlock_disabled

 
12/08/2026 15:30:28 DVSim: v1.50.1 sha: 71b9f97 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.05 %
  • code
  • 83.44 %
  • assert
  • 94.41 %
  • func
  • 92.29 %
  • line
  • 97.20 %
  • branch
  • 93.70 %
  • cond
  • 79.22 %
  • toggle
  • 86.33 %
  • FSM
  • 60.75 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.480s 244.971us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 0.810s 81.416us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.850s 18.049us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.370s 125.165us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.160s 42.404us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.110s 34.963us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.850s 18.049us 1 1 100.00
lc_ctrl_csr_aliasing 1.160s 42.404us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 4.070s 87.823us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 9.630s 661.339us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.980s 13.883us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 1.900s 56.706us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 7.690s 979.839us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 6.620s 964.425us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 7.690s 979.839us 1 1 100.00
lc_ctrl_prog_failure 1.900s 56.706us 1 1 100.00
lc_ctrl_errors 6.620s 964.425us 1 1 100.00
lc_ctrl_security_escalation 4.930s 219.500us 1 1 100.00
lc_ctrl_jtag_state_failure 16.030s 6493.233us 1 1 100.00
lc_ctrl_jtag_prog_failure 3.010s 254.696us 1 1 100.00
lc_ctrl_jtag_errors 11.050s 1333.702us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 3.670s 1173.593us 1 1 100.00
lc_ctrl_jtag_state_post_trans 9.080s 3490.180us 1 1 100.00
lc_ctrl_jtag_prog_failure 3.010s 254.696us 1 1 100.00
lc_ctrl_jtag_errors 11.050s 1333.702us 1 1 100.00
lc_ctrl_jtag_access 3.310s 3401.772us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 13.270s 1226.194us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 1.010s 45.820us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.460s 179.596us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 4.250s 2453.525us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 4.700s 1524.075us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.200s 78.910us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 2.140s 913.930us 1 1 100.00
lc_ctrl_jtag_alert_test 1.090s 281.425us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 4.060s 1956.838us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.810s 16.193us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 171.790s 77886.800us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 1.130s 22.129us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 1.360s 34.532us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 1.360s 34.532us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.810s 81.416us 1 1 100.00
lc_ctrl_csr_rw 0.850s 18.049us 1 1 100.00
lc_ctrl_csr_aliasing 1.160s 42.404us 1 1 100.00
lc_ctrl_same_csr_outstanding 0.890s 17.981us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.810s 81.416us 1 1 100.00
lc_ctrl_csr_rw 0.850s 18.049us 1 1 100.00
lc_ctrl_csr_aliasing 1.160s 42.404us 1 1 100.00
lc_ctrl_same_csr_outstanding 0.890s 17.981us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 5.300s 136.043us 1 1 100.00
lc_ctrl_tl_intg_err 1.200s 587.430us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.200s 587.430us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 9.630s 661.339us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 7.690s 979.839us 1 1 100.00
lc_ctrl_sec_cm 5.300s 136.043us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 7.690s 979.839us 1 1 100.00
lc_ctrl_sec_cm 5.300s 136.043us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 7.690s 979.839us 1 1 100.00
lc_ctrl_sec_cm 5.300s 136.043us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 7.690s 979.839us 1 1 100.00
lc_ctrl_sec_cm 5.300s 136.043us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 7.690s 979.839us 1 1 100.00
lc_ctrl_sec_cm 5.300s 136.043us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 7.690s 979.839us 1 1 100.00
lc_ctrl_sec_cm 5.300s 136.043us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 7.690s 979.839us 1 1 100.00
lc_ctrl_sec_cm 5.300s 136.043us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 7.690s 979.839us 1 1 100.00
lc_ctrl_sec_cm 5.300s 136.043us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 4.930s 219.500us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 4.070s 87.823us 1 1 100.00
lc_ctrl_jtag_state_post_trans 9.080s 3490.180us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 4.440s 1097.416us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 4.440s 1097.416us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 4.940s 1485.628us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.620s 228.237us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.620s 228.237us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 22.910s 7443.397us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1286) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
lc_ctrl_stress_all_with_rand_reset 115416739160469975259115457170789325109736030215780383659177575430275188203822 8983
UVM_INFO @ 7443397253 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---