Simulation Results: lc_ctrl/volatile_unlock_enabled

 
12/08/2026 15:30:28 DVSim: v1.50.1 sha: 71b9f97 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 89.85 %
  • code
  • 83.12 %
  • assert
  • 94.13 %
  • func
  • 92.29 %
  • line
  • 97.13 %
  • branch
  • 93.37 %
  • cond
  • 79.47 %
  • toggle
  • 84.88 %
  • FSM
  • 60.75 %
Validation stages
V1
100.00%
V2
96.67%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.810s 48.025us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 0.810s 36.547us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.850s 15.977us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 2.000s 525.710us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.120s 72.109us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.160s 61.369us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.850s 15.977us 1 1 100.00
lc_ctrl_csr_aliasing 1.120s 72.109us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 3.790s 381.324us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 4.890s 1302.610us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.820s 13.805us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 1.960s 560.489us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 7.290s 2299.657us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 4.660s 331.509us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 7.290s 2299.657us 1 1 100.00
lc_ctrl_prog_failure 1.960s 560.489us 1 1 100.00
lc_ctrl_errors 4.660s 331.509us 1 1 100.00
lc_ctrl_security_escalation 4.580s 338.901us 1 1 100.00
lc_ctrl_jtag_state_failure 27.670s 12445.070us 1 1 100.00
lc_ctrl_jtag_prog_failure 3.950s 298.504us 1 1 100.00
lc_ctrl_jtag_errors 14.660s 15174.905us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 2.530s 165.992us 1 1 100.00
lc_ctrl_jtag_state_post_trans 4.620s 1479.955us 1 1 100.00
lc_ctrl_jtag_prog_failure 3.950s 298.504us 1 1 100.00
lc_ctrl_jtag_errors 14.660s 15174.905us 1 1 100.00
lc_ctrl_jtag_access 4.440s 1924.519us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 9.050s 8983.564us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 1.010s 419.305us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.160s 73.089us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 3.130s 1361.922us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 2.800s 363.018us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.120s 54.955us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 1.890s 50.851us 1 1 100.00
lc_ctrl_jtag_alert_test 0.910s 216.933us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 26.400s 10586.203us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.940s 14.648us 1 1 100.00
stress_all 0 1 0.00
lc_ctrl_stress_all 16.220s 29909.276us 0 1 0.00
alert_test 1 1 100.00
lc_ctrl_alert_test 0.810s 23.276us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 1.110s 81.555us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 1.110s 81.555us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.810s 36.547us 1 1 100.00
lc_ctrl_csr_rw 0.850s 15.977us 1 1 100.00
lc_ctrl_csr_aliasing 1.120s 72.109us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.090s 17.584us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.810s 36.547us 1 1 100.00
lc_ctrl_csr_rw 0.850s 15.977us 1 1 100.00
lc_ctrl_csr_aliasing 1.120s 72.109us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.090s 17.584us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 5.730s 248.148us 1 1 100.00
lc_ctrl_tl_intg_err 1.440s 124.721us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.440s 124.721us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 4.890s 1302.610us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 7.290s 2299.657us 1 1 100.00
lc_ctrl_sec_cm 5.730s 248.148us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 7.290s 2299.657us 1 1 100.00
lc_ctrl_sec_cm 5.730s 248.148us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 7.290s 2299.657us 1 1 100.00
lc_ctrl_sec_cm 5.730s 248.148us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 7.290s 2299.657us 1 1 100.00
lc_ctrl_sec_cm 5.730s 248.148us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 7.290s 2299.657us 1 1 100.00
lc_ctrl_sec_cm 5.730s 248.148us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 7.290s 2299.657us 1 1 100.00
lc_ctrl_sec_cm 5.730s 248.148us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 7.290s 2299.657us 1 1 100.00
lc_ctrl_sec_cm 5.730s 248.148us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 7.290s 2299.657us 1 1 100.00
lc_ctrl_sec_cm 5.730s 248.148us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 4.580s 338.901us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 3.790s 381.324us 1 1 100.00
lc_ctrl_jtag_state_post_trans 4.620s 1479.955us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 4.990s 1039.015us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 4.990s 1039.015us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 8.230s 585.866us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 6.490s 1738.225us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 6.490s 1738.225us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
lc_ctrl_stress_all_with_rand_reset 16.970s 5624.767us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (* [*] vs * [*]) 1 test run
lc_ctrl_stress_all 56947402249775776853765792602778225023338469720002647742410608727838878131693 4199
UVM_INFO @ 29909276389 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---