Simulation Results: pwrmgr

 
12/08/2026 15:30:28 DVSim: v1.50.1 sha: 71b9f97 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.32 %
  • code
  • 95.61 %
  • assert
  • 98.17 %
  • func
  • 98.19 %
  • line
  • 99.09 %
  • branch
  • 96.37 %
  • cond
  • 95.62 %
  • toggle
  • 90.96 %
  • FSM
  • 96.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
pwrmgr_smoke 0.620s 23.713us 1 1 100.00
csr_hw_reset 1 1 100.00
pwrmgr_csr_hw_reset 0.710s 33.279us 1 1 100.00
csr_rw 1 1 100.00
pwrmgr_csr_rw 0.620s 51.286us 1 1 100.00
csr_bit_bash 1 1 100.00
pwrmgr_csr_bit_bash 2.940s 341.852us 1 1 100.00
csr_aliasing 1 1 100.00
pwrmgr_csr_aliasing 0.990s 81.786us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
pwrmgr_csr_mem_rw_with_rand_reset 0.960s 112.334us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
pwrmgr_csr_rw 0.620s 51.286us 1 1 100.00
pwrmgr_csr_aliasing 0.990s 81.786us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
wakeup 1 1 100.00
pwrmgr_wakeup 0.750s 85.849us 1 1 100.00
control_clks 1 1 100.00
pwrmgr_wakeup 0.750s 85.849us 1 1 100.00
aborted_low_power 2 2 100.00
pwrmgr_aborted_low_power 0.780s 152.507us 1 1 100.00
pwrmgr_lowpower_invalid 0.670s 71.643us 1 1 100.00
reset 2 2 100.00
pwrmgr_reset 0.770s 78.332us 1 1 100.00
pwrmgr_reset_invalid 0.710s 167.347us 1 1 100.00
main_power_glitch_reset 1 1 100.00
pwrmgr_reset 0.770s 78.332us 1 1 100.00
reset_wakeup_race 1 1 100.00
pwrmgr_wakeup_reset 0.730s 182.651us 1 1 100.00
lowpower_wakeup_race 1 1 100.00
pwrmgr_lowpower_wakeup_race 1.000s 259.388us 1 1 100.00
disable_rom_integrity_check 1 1 100.00
pwrmgr_disable_rom_integrity_check 0.830s 72.047us 1 1 100.00
stress_all 1 1 100.00
pwrmgr_stress_all 1.340s 460.434us 1 1 100.00
intr_test 1 1 100.00
pwrmgr_intr_test 0.620s 18.653us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
pwrmgr_tl_errors 1.240s 229.546us 1 1 100.00
tl_d_illegal_access 1 1 100.00
pwrmgr_tl_errors 1.240s 229.546us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
pwrmgr_csr_hw_reset 0.710s 33.279us 1 1 100.00
pwrmgr_csr_rw 0.620s 51.286us 1 1 100.00
pwrmgr_csr_aliasing 0.990s 81.786us 1 1 100.00
pwrmgr_same_csr_outstanding 0.860s 42.678us 1 1 100.00
tl_d_partial_access 4 4 100.00
pwrmgr_csr_hw_reset 0.710s 33.279us 1 1 100.00
pwrmgr_csr_rw 0.620s 51.286us 1 1 100.00
pwrmgr_csr_aliasing 0.990s 81.786us 1 1 100.00
pwrmgr_same_csr_outstanding 0.860s 42.678us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
pwrmgr_tl_intg_err 0.960s 111.481us 1 1 100.00
pwrmgr_sec_cm 0.980s 1008.405us 1 1 100.00
prim_count_check 1 1 100.00
pwrmgr_sec_cm 0.980s 1008.405us 1 1 100.00
prim_fsm_check 1 1 100.00
pwrmgr_sec_cm 0.980s 1008.405us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
pwrmgr_tl_intg_err 0.960s 111.481us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_lc_ctrl_intersig_mubi 1.740s 1305.859us 1 1 100.00
sec_cm_rom_ctrl_intersig_mubi 2 2 100.00
pwrmgr_wakeup_reset 0.730s 182.651us 1 1 100.00
pwrmgr_repeat_wakeup_reset 2.380s 763.833us 1 1 100.00
sec_cm_rstmgr_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_rstmgr_intersig_mubi 0.760s 83.687us 1 1 100.00
sec_cm_esc_rx_clk_bkgn_chk 1 1 100.00
pwrmgr_esc_clk_rst_malfunc 0.650s 54.539us 1 1 100.00
sec_cm_esc_rx_clk_local_esc 1 1 100.00
pwrmgr_sec_cm 0.980s 1008.405us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
pwrmgr_sec_cm 0.980s 1008.405us 1 1 100.00
sec_cm_fsm_terminal 1 1 100.00
pwrmgr_sec_cm 0.980s 1008.405us 1 1 100.00
sec_cm_ctrl_flow_global_esc 1 1 100.00
pwrmgr_global_esc 0.590s 87.348us 1 1 100.00
sec_cm_main_pd_rst_local_esc 1 1 100.00
pwrmgr_glitch 0.640s 44.806us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
pwrmgr_sec_cm_ctrl_config_regwen 0.630s 27.663us 1 1 100.00
sec_cm_wakeup_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.620s 51.286us 1 1 100.00
sec_cm_reset_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.620s 51.286us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
escalation_timeout 1 1 100.00
pwrmgr_escalation_timeout 0.830s 294.052us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
pwrmgr_stress_all_with_rand_reset 11.250s 15148.662us 1 1 100.00