Simulation Results: rom_ctrl/32kb

 
12/08/2026 15:30:28 DVSim: v1.50.1 sha: 71b9f97 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 94.33 %
  • code
  • 88.21 %
  • assert
  • 97.68 %
  • func
  • 97.11 %
  • line
  • 97.88 %
  • branch
  • 98.54 %
  • cond
  • 95.99 %
  • toggle
  • 95.31 %
  • FSM
  • 53.33 %
Validation stages
V1
100.00%
V2
88.89%
V2S
83.33%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 3.860s 227.367us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 2.860s 64.449us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 1.760s 65.373us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 2.110s 253.945us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 1.870s 82.656us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 2.590s 104.422us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 1.760s 65.373us 1 1 100.00
rom_ctrl_csr_aliasing 1.870s 82.656us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 1.830s 56.068us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 2.000s 51.469us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 0 1 0.00
rom_ctrl_max_throughput_chk 1.960s 16.973us 0 1 0.00
stress_all 1 1 100.00
rom_ctrl_stress_all 8.740s 571.898us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 2.880s 58.180us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 1.960s 60.312us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 4.570s 381.874us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 4.570s 381.874us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 2.860s 64.449us 1 1 100.00
rom_ctrl_csr_rw 1.760s 65.373us 1 1 100.00
rom_ctrl_csr_aliasing 1.870s 82.656us 1 1 100.00
rom_ctrl_same_csr_outstanding 2.150s 154.612us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 2.860s 64.449us 1 1 100.00
rom_ctrl_csr_rw 1.760s 65.373us 1 1 100.00
rom_ctrl_csr_aliasing 1.870s 82.656us 1 1 100.00
rom_ctrl_same_csr_outstanding 2.150s 154.612us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.120s 0.000us 0 1 0.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 7.300s 148.065us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 200.560s 1919.071us 1 1 100.00
rom_ctrl_tl_intg_err 43.190s 1154.316us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 200.560s 1919.071us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 200.560s 1919.071us 1 1 100.00
sec_cm_checker_ctr_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.120s 0.000us 0 1 0.00
sec_cm_checker_ctrl_flow_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.120s 0.000us 0 1 0.00
sec_cm_checker_fsm_local_esc 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.120s 0.000us 0 1 0.00
sec_cm_compare_ctrl_flow_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.120s 0.000us 0 1 0.00
sec_cm_compare_ctr_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.120s 0.000us 0 1 0.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 200.560s 1919.071us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 200.560s 1919.071us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 3.860s 227.367us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 3.860s 227.367us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 3.860s 227.367us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 43.190s 1154.316us 1 1 100.00
sec_cm_bus_local_esc 1 2 50.00
rom_ctrl_corrupt_sig_fatal_chk 3600.120s 0.000us 0 1 0.00
rom_ctrl_kmac_err_chk 2.880s 58.180us 1 1 100.00
sec_cm_mux_mubi 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.120s 0.000us 0 1 0.00
sec_cm_mux_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.120s 0.000us 0 1 0.00
sec_cm_ctrl_redun 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.120s 0.000us 0 1 0.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 7.300s 148.065us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 200.560s 1919.071us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 190.440s 15033.049us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (rom_ctrl_throughput_vseq.sv:52) [rom_ctrl_throughput_vseq] Check failed num_cycles == num_mem_reads + * (* [*] vs * [*]) 1 test run
rom_ctrl_max_throughput_chk 115433130263241428114941880835475278797025647712309802936232741362532481807803 85
UVM_INFO @ 16972644 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes 1 test run
rom_ctrl_corrupt_sig_fatal_chk 97410707774581338492713049702614960651526985675331363884573255410525472850855 None