Simulation Results: rom_ctrl/64kb

 
12/08/2026 15:30:28 DVSim: v1.50.1 sha: 71b9f97 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.49 %
  • code
  • 92.46 %
  • assert
  • 96.66 %
  • func
  • 97.35 %
  • line
  • 98.81 %
  • branch
  • 97.81 %
  • cond
  • 97.03 %
  • toggle
  • 95.34 %
  • FSM
  • 73.33 %
Validation stages
V1
100.00%
V2
88.89%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 6.390s 470.362us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 8.230s 78.101us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 5.330s 87.706us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 4.430s 129.919us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 3.650s 61.440us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 3.940s 57.724us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 5.330s 87.706us 1 1 100.00
rom_ctrl_csr_aliasing 3.650s 61.440us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 4.080s 74.217us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 3.030s 72.234us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 0 1 0.00
rom_ctrl_max_throughput_chk 5.920s 1495.535us 0 1 0.00
stress_all 1 1 100.00
rom_ctrl_stress_all 21.900s 1425.665us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 8.500s 383.538us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 3.490s 59.611us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 10.420s 715.096us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 10.420s 715.096us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 8.230s 78.101us 1 1 100.00
rom_ctrl_csr_rw 5.330s 87.706us 1 1 100.00
rom_ctrl_csr_aliasing 3.650s 61.440us 1 1 100.00
rom_ctrl_same_csr_outstanding 4.030s 94.788us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 8.230s 78.101us 1 1 100.00
rom_ctrl_csr_rw 5.330s 87.706us 1 1 100.00
rom_ctrl_csr_aliasing 3.650s 61.440us 1 1 100.00
rom_ctrl_same_csr_outstanding 4.030s 94.788us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 121.620s 6478.023us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 28.270s 2186.358us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 471.520s 1203.325us 1 1 100.00
rom_ctrl_tl_intg_err 49.870s 325.197us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 471.520s 1203.325us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 471.520s 1203.325us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 121.620s 6478.023us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 121.620s 6478.023us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 121.620s 6478.023us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 121.620s 6478.023us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 121.620s 6478.023us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 471.520s 1203.325us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 471.520s 1203.325us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 6.390s 470.362us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 6.390s 470.362us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 6.390s 470.362us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 49.870s 325.197us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 121.620s 6478.023us 1 1 100.00
rom_ctrl_kmac_err_chk 8.500s 383.538us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 121.620s 6478.023us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 121.620s 6478.023us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 121.620s 6478.023us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 28.270s 2186.358us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 471.520s 1203.325us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 131.150s 34066.878us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (rom_ctrl_throughput_vseq.sv:52) [rom_ctrl_throughput_vseq] Check failed num_cycles == num_mem_reads + * (* [*] vs * [*]) 1 test run
rom_ctrl_max_throughput_chk 77453836179840392827458101893605111329513036221692776133802508592998827603083 85
UVM_INFO @ 1495534567 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---