Simulation Results: rstmgr

 
12/08/2026 15:30:28 DVSim: v1.50.1 sha: 71b9f97 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.74 %
  • code
  • 99.31 %
  • assert
  • 98.66 %
  • func
  • 98.26 %
  • line
  • 99.51 %
  • branch
  • 99.83 %
  • cond
  • 98.89 %
  • toggle
  • 99.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rstmgr_smoke 1.140s 139.069us 1 1 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 1.160s 150.500us 1 1 100.00
csr_rw 1 1 100.00
rstmgr_csr_rw 0.840s 75.777us 1 1 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 5.080s 700.702us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 2.230s 409.917us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rstmgr_csr_mem_rw_with_rand_reset 1.280s 213.497us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rstmgr_csr_rw 0.840s 75.777us 1 1 100.00
rstmgr_csr_aliasing 2.230s 409.917us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 1 1 100.00
rstmgr_por_stretcher 0.860s 171.205us 1 1 100.00
sw_rst 1 1 100.00
rstmgr_sw_rst 1.940s 487.784us 1 1 100.00
sw_rst_reset_race 1 1 100.00
rstmgr_sw_rst_reset_race 0.960s 126.980us 1 1 100.00
reset_info 1 1 100.00
rstmgr_reset 3.860s 1099.991us 1 1 100.00
cpu_info 1 1 100.00
rstmgr_reset 3.860s 1099.991us 1 1 100.00
alert_info 1 1 100.00
rstmgr_reset 3.860s 1099.991us 1 1 100.00
reset_info_capture 1 1 100.00
rstmgr_reset 3.860s 1099.991us 1 1 100.00
stress_all 1 1 100.00
rstmgr_stress_all 42.890s 17797.550us 1 1 100.00
alert_test 1 1 100.00
rstmgr_alert_test 1.120s 270.859us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rstmgr_tl_errors 2.760s 552.700us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rstmgr_tl_errors 2.760s 552.700us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rstmgr_csr_hw_reset 1.160s 150.500us 1 1 100.00
rstmgr_csr_rw 0.840s 75.777us 1 1 100.00
rstmgr_csr_aliasing 2.230s 409.917us 1 1 100.00
rstmgr_same_csr_outstanding 0.990s 153.789us 1 1 100.00
tl_d_partial_access 4 4 100.00
rstmgr_csr_hw_reset 1.160s 150.500us 1 1 100.00
rstmgr_csr_rw 0.840s 75.777us 1 1 100.00
rstmgr_csr_aliasing 2.230s 409.917us 1 1 100.00
rstmgr_same_csr_outstanding 0.990s 153.789us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rstmgr_sec_cm 19.100s 17390.174us 1 1 100.00
rstmgr_tl_intg_err 1.810s 508.574us 1 1 100.00
prim_count_check 1 1 100.00
rstmgr_sec_cm 19.100s 17390.174us 1 1 100.00
prim_fsm_check 1 1 100.00
rstmgr_sec_cm 19.100s 17390.174us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rstmgr_tl_intg_err 1.810s 508.574us 1 1 100.00
sec_cm_scan_intersig_mubi 1 1 100.00
rstmgr_sec_cm_scan_intersig_mubi 0.920s 119.452us 1 1 100.00
sec_cm_leaf_rst_bkgn_chk 1 1 100.00
rstmgr_leaf_rst_cnsty 5.530s 1415.206us 1 1 100.00
sec_cm_leaf_rst_shadow 1 1 100.00
rstmgr_leaf_rst_shadow_attack 1.050s 302.444us 1 1 100.00
sec_cm_leaf_fsm_sparse 1 1 100.00
rstmgr_sec_cm 19.100s 17390.174us 1 1 100.00
sec_cm_sw_rst_config_regwen 1 1 100.00
rstmgr_csr_rw 0.840s 75.777us 1 1 100.00
sec_cm_dump_ctrl_config_regwen 1 1 100.00
rstmgr_csr_rw 0.840s 75.777us 1 1 100.00